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| DATA SHEET MOS INTEGRATED CIRCUIT PD61051, 61052 MPEG2 AUDIO/VIDEO ENCODER The PD61051 and PD61052 are LSIs of MPEG audio and video encoding, decoding and transcoding. The PD61051 has MPEG2 video encoder, MPEG audio encoding DSP, 32-bit RISC CPU, video input/output unit which contains a processing filter and a time base corrector (TBC), and MPEG system layer which contains the multiplexer and de-multiplexer. It combines with 64 M or 128 Mbit SDRAM and it uses. The PD61052 has a DolbyTM Digital Consumer Encoder in addition to the PD61051. The PD61051, 61052 are the optimal choice for consumer digital video recording replay equipment to process a MPEG. FEATURES * Video encode - Stream standard: MPEG2 video MP@ML, SP@ML standard, MPEG1 standard Picture size: Horizontal: 720, 704, 544, 480, 352 dots/line Vertical: 480, 240, 576, 288 line/frame Bit rate conversion, VBR CBR Single pass variable bit rate (VBR), constant bit rate (CBR) encoding Transcoding: * Video input/output Format: 8-bit Y/Cb/Cr 4:2:2 (ITU-R BT.656) Pre analysis: Film detect, scene changing detect, and motion estimation assist TBC, VBI data slicer Audio encoding - Bit length: 16 bits, 20 bits, 24 bits - Sampling rate: 32 kHz, 44.1 kHz, 48 kHz - MPEG1 audio layer 2 standard based - Dolby Digital Consumer Encoder standard based (Only the PD61052) - Elementary stream and PCM audio input/output MPEG system processing * - Multiplex: MPEG2-PS, MPEG2-TS, DVD-Video, and DVD-VR - De-multiplex: MPEG2-PS, MPEG2-TS - Transcoding: MPEG2 format conversion (MPEG2-TS MPEG2-PS) - Partial TS generation Package: 208-pin fine pitch QFP Power supply: 1200 mW (Typ.) Power supply voltage: 3.30.165 V, 2.50.2 V (Internal circuit power) "Dolby" is a trademark of Dolby Laboratories. To use the PD61052, a license from Dolby Laboratories Licensing Corporation is necessary. * * * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15082EJ4V0DS00 (4th edition) Date Published November 2003 NS CP (K) Printed in Japan The mark shows major revised points. 2002 PD61051, 61052 APPLICATION D-VHS, DVD video recorder, HDD video recorder ORDERING INFORMATION Part Number Package 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) PD61051GD-LML Note PD61051GD-LML-A PD61052GD-LML Note PD61052GD-LML-A Note Lead-free product BLOCK DIAGRAM OVOUT7-OVOUT0/FA19-FA14 MCLKE MCLK MCS MRAS MCAS MWE MA13-MA0 MD31-MD0 MDQM CCS CRE CWE/CSDI CA5-CA0/FA5-FA0 CD7-CD0/FD7-FD0 CWAIT/FOE CINT CMODE1/CSDO CMODE0/CSCLK IVCLK IVIN7-IVIN0 IVFLD IVVSYNC IVHSYNC OVCLK Video Input Unit SDRAM Interface Unit Video Output Unit Host CPU Interface Unit CMODE2 GPO6/OVVSYNC GPO5/OVHSYNC GPIO4-GPIO0 Internal CPU OSREQ OSVLD/OSRDY OSSYNC OSCLK/OSSTB OS7-OS0/FA13-FA6 Stream Interface Unit Video Encode/Transcode Unit PSTOP SCLK (27 MHz) PLL Audio DSP Engine System Control Unit ISREQ ISVLD ISCLK/ISSTB IS7-IS2 IS1/ISERR IS0 STCLK IABD IABCK IALRCK OABD OABCK OALRCK AMCLK 2 Data Sheet S15082EJ4V0DS RESET PWM PD61051, 61052 PERIPHERAL CONNECTION SDRAM SDRAM Video Input Audio Input NTSC/PAL Decoder BT.656 MPEG2 AV Encoder PD61051/61052 PCM TS Decoder MPEG Decoder Video Output PCM Audio Output ADC DAC Host CPU 1394 In/Out 1394 PHY 1394 AV Link TS Stream Interface AV HDD Data Sheet S15082EJ4V0DS 3 PD61051, 61052 This LSI deals with two kinds of methods to connect a system controller. Parallel Bus Interface 64M SDRAM NTSC/PAL Decoder BT.656 PD61051/61052 BT.656 NTSC/PAL Encoder Audio ADC/DAC Audio ADC PCM 27 MHz STC Clock PCM MPEG TS/PS MPEG TS/PS User Interface Host CPU Serial Bus Interface 64M SDRAM NTSC/PAL Decoder BT.656 PD61051/61052 BT.656 NTSC/PAL Encoder Audio ADC/DAC Audio ADC PCM 27 MHz STC Clock PCM MPEG TS/PS MPEG TS/PS User Interface SPI Host CPU Instruction ROM 4 Data Sheet S15082EJ4V0DS PD61051, 61052 PIN CONFIGURATION (TOP VIEW) * 208-pin plastic QFP (Fine pitch) (28x28) PD61051GD-LML PD61051GD-LML-A PD61052GD-LML PD61052GD-LML-A OVOUT7 OVOUT6 OVOUT5/FA19 OVOUT4/FA18 OVOUT3/FA17 OVOUT2/FA16 OVOUT1/FA15 OVOUT0/FA14 GND OVCLK VDD2 GPO6/OVVSYNC GND GPO5/OVHSYNC VDD3 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GND CA5/FA5 VDD2 CA4/FA4 CA3/FA3 CA2/FA2 CA1/FA1 CA0/FA0 NDO NDI NMOD GND NRST VDD2 NCLK GND CD7/FD7 VDD3 CD6/FD6 CD5/FD5 CD4/FD4 CD3/FD3 CD2/FD2 GND CD1/FD1 VDD2 CD0/FD0 CWAIT/FOE CRE CCS CMODE2 CWE/CSDI 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VDD2 AMCLK GND OALRCK OABCK OABD IALRCK IABCK IABD GND IVFLD IVHSYNC VDD2 IVVSYNC GND IVIN0 IVIN1 IVIN2 IVIN3 IVIN4 IVIN5 IVIN6 IVIN7 VDD2 IVCLK GND GND SCLK PSTOP PVDD2 PGND PVDD2 PGND STCLK GND VDD2 GND GND VDD3 PWM GND IS0 IS1/ISERR IS2 IS3 IS4 IS5 VDD2 IS6 GND IS7 ISSYNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 CMODE1/CSDO CMODE0/CSCLK GND CINT VDD2 RESET GND MD15 VDD3 MD14 MD13 MD12 MD11 MD10 GND MD9 VDD2 MD8 MD0 GND MD1 VDD3 MD2 MD3 MD4 MD5 GND MD6 VDD2 MD7 MDQM MWE GND MCAS VDD3 MRAS MCS GND MCLK VDD2 MCLKE MA11 MA9 MA8 GND MA7 VDD3 MA6 MA5 GND MA4 VDD2 ISCLK/ISSTB ISVLD ISREQ OS0/FA6 OS1/FA7 OS2/FA8 OS3/FA9 VDD2 OS4/FA10 GND OS5/FA11 OS6/FA12 OS7/FA13 OSCLK/OSSTB OSSYNC OSVLD/OSRDY VDD3 OSREQ VDD2 MD23 GND GND MD22 MD21 MD20 MD19 MD18 MD17 MD16 VDD2 MD24 GND MD25 VDD3 MD26 GND MD27 MD28 MD29 MD30 MD31 VDD2 MA0 GND MA1 VDD3 MA2 GND MA3 MA10 MA12 MA13 Data Sheet S15082EJ4V0DS 5 PD61051, 61052 PIN LIST AMCLK CA0/FA0 to CA5/FA5 :Audio Main Clock :Host CPU Address/ Instruction ROM Address CCS :Host CPU Chip Select MA0 to MA13 MCAS MCLK MCLKE MCS MD0 to MD31 MDQM MRAS MWE NCLK NDI NDO NMOD NRST OABCK OABD OALRCK :Memory Address :Memory Column Address Strobe :Memory Clock :Memory Clock Enable :Memory Chip Select :Memory Data :Memory DQ Mask Enable :Memory Row Address Strobe :Memory Write Enable :N-wire Clock :N-wire Data Input :N-wire Data Output :N-wire Mode :N-wire Reset :Output Audio Bit Clock :Output Audio Bit Data :Output Audio LR Clock CD0/FD0 to CD7/FD7 :Host CPU Data/ Instruction ROM Data CINT CMODE0/CSCLK :Host CPU Interrupt :Host CPU Mode/ SPI Clock CMODE1/CSDO :Host CPU Mode/ SPI Data Output CMODE2 CRE CWAIT/FOE :Host CPU Mode :Host CPU Read Enable :Host CPU Wait/ Instruction ROM Output Enable CWE/CSDI :Host CPU Write Enable/ SPI Data Input GND GPIO0 to GPIO4 GPO5/OVHSYNC :Ground :General Purpose IO :General Purpose Output/ Output Video Horizontal Sync GPO6/OVVSYNC :General Purpose Output/ Output Video Vertical Sync IABCK IABD IALRCK IS0, IS2 to IS7 IS1/ISERR ISCLK/ISSTB :Input Audio Bit Clock :Input Audio Bit Data :Input Audio LR Clock :Input Stream Data :Input Stream Data/ Input Stream Error :Input Stream Data Clock/ Input Stream Data Strobe ISREQ ISSYNC ISVLD IVCLK IVFLD IVHSYNC IVIN0 to IVIN7 IVVSYNC :Input Stream Data Request :Input Stream Data Sync :Input Stream Data Valid :Input Video Clock :Input Video Field Index :Input Video Horizontal Sync :Input Video Data :Input Video Vertical Sync OS0/FA6 to OS7/FA13 :Output Stream Data/ Instruction ROM Address OSCLK/OSSTB :Output Stream Data Clock/ Output Stream Data Strobe OSREQ OSSYNC OSVLD/OSRDY :Output Stream Data Request :Output Stream Data Sync :Output Stream Data Valid/ Output Stream Data Ready OVCLK OVOUT0/FA14 to OVOUT5/FA19 OVOUT6,OVOUT7 PGND PSTOP PVDD2 PWM RESET SCLK STCLK VDD2 VDD3 :Output Video Clock :Output Video Data/ Instruction ROM Address :Output Video Data :PLL Ground :PLL Stop :PLL 2.5 V Power Supply :PWM Output :Reset :System Clock :System Time Clock :2.5 V Power Supply :3.3 V Power Supply 6 Data Sheet S15082EJ4V0DS PD61051, 61052 CONTENTS 1. PIN FUNCTION ............................................................................................................................... 9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Video Input Interface............................................................................................................................. 9 Video Output Interface.......................................................................................................................... 9 Audio Input Interface ............................................................................................................................ 9 Audio Input/output Interface .............................................................................................................. 10 Stream Input Interface ........................................................................................................................ 10 Stream Output Interface ..................................................................................................................... 11 SDRAM Interface ................................................................................................................................. 11 Host CPU Interface.............................................................................................................................. 12 1.8.1 1.8.2 1.9 Parallel bus interface................................................................................................................. 12 Serial bus interface.................................................................................................................... 12 Clock, Reset......................................................................................................................................... 13 1.10 N-Wire................................................................................................................................................... 13 1.11 GPIO ..................................................................................................................................................... 14 1.12 Power Supply ...................................................................................................................................... 14 1.13 Recommended Connections of Unused Pins ................................................................................... 15 2. FEATURE OVERVIEW.................................................................................................................. 16 2.1 Video .................................................................................................................................................... 16 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.5 2.6 2.7 2.8 Encoding ................................................................................................................................... 16 Transcoding............................................................................................................................... 16 Input/output processing ............................................................................................................. 17 Encoding ................................................................................................................................... 19 Transcoding (DEMUX, MUX) .................................................................................................... 19 Input/output processing ............................................................................................................. 19 System time clock ..................................................................................................................... 22 Multiplex .................................................................................................................................... 23 De-multiplex .............................................................................................................................. 23 Transcode ................................................................................................................................. 24 Parallel steam data interface ..................................................................................................... 25 Serial stream data interface....................................................................................................... 29 Audio .................................................................................................................................................... 19 MPEG System Processing.................................................................................................................. 22 Stream Interface .................................................................................................................................. 25 Host CPU Interface.............................................................................................................................. 32 SDRAM Interface ................................................................................................................................. 33 Memory Connection Diagram ............................................................................................................ 34 Memory Map ........................................................................................................................................ 36 3. SYSTEM INTERFACE REGISTER .............................................................................................. 38 3.1 3.2 Register Mapping (General Mapping)................................................................................................ 39 Register Functions.............................................................................................................................. 40 3.2.1 3.2.2 3.2.3 3.2.4 Common register....................................................................................................................... 40 Data transfer register................................................................................................................. 40 Internal CPU interrupt register................................................................................................... 47 Interrupt mask register .............................................................................................................. 47 Data Sheet S15082EJ4V0DS 7 PD61051, 61052 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 Download interrupt register ....................................................................................................... 47 Interrupt register ........................................................................................................................ 48 Reset register ............................................................................................................................ 48 ROM access cycle register........................................................................................................ 49 Port setup register ..................................................................................................................... 49 4. SYSTEM INTERFACE PROCEDURE.......................................................................................... 50 4.1 4.2 Outline .................................................................................................................................................. 51 Firmware Download ............................................................................................................................ 52 4.2.1 4.2.2 4.2.3 4.2.4 4.3 4.4 4.5 4.6 4.7 4.8 Host CPU to instruction RAM of internal CPU ........................................................................... 52 External ROM to instruction RAM of internal CPU..................................................................... 53 Host CPU to SDRAM................................................................................................................. 54 External ROM to SDRAM .......................................................................................................... 55 SDRAM Write during Executing ......................................................................................................... 56 SDRAM Read during Executing ......................................................................................................... 57 SDRAM Initialization............................................................................................................................ 58 Operation Mode Setting by Changing Firmware .............................................................................. 59 Transfer Ending................................................................................................................................... 60 Transfer Error Handling ...................................................................................................................... 61 4.8.1 4.8.2 4.8.3 Transfer error handling 1 ........................................................................................................... 61 Transfer error handling 2 ........................................................................................................... 62 Transfer error handling 3 ........................................................................................................... 63 5. EXAMPLE FOR COMMON REGISTER USAGE....................................................................... 64 5.1 5.2 Register Map Example ........................................................................................................................ 65 Example of the Common Register Which A Firmware Defines ....................................................... 67 5.2.1 5.2.2 COMCODE: Command code register........................................................................................ 66 ESTS: Status register ................................................................................................................ 66 6. ELECTRICAL CHARACTERISTICS............................................................................................. 68 7. PACKAGE DRAWING ................................................................................................................ 102 8. RECOMMENDED SOLDERING CONDITIONS......................................................................... 103 8 Data Sheet S15082EJ4V0DS PD61051, 61052 1. PIN FUNCTION Sharing pin is bold faced in name and explains the feature shown. 1.1 Video Input Interface The video input is based on the ITU-R BT.656 format. The horizontal synchronization signal, and the vertical synchronization signal, the field index can be used without using SAV and EAV to provide at ITU-R BT. 656, too. Name IO Pin Number IVIN7 to IVIN0 IVCLK IVHSYNC IVVSYNC IVFLD I I I I I 23 to 16 25 12 14 11 Video data Video clock (27 MHz) Horizontal synchronization Vertical synchronization Field index L L Function Active Polarity 1.2 Video Output Interface The video output is based on the ITU-R BT.656 format. It is able to output horizontal and vertical synchronization signals with SAV/EAV. These synchronization signals are chosen output by the firmware. These ports become GPO until the firmware initializes after hardware reset. At the time of the odd field, OVVSYNC falls in the 4th clock after falling of OVHSYNC. At the time of the even field, OVVSYNC falls in to the H/2+4th clock the OVHSYNC falling. Name IO Pin Number OVOUT7, OVOUT6 OVOUT5 to OVOUT0/ FA19 to FA14 OVCLK GPO5/OVHSYNC GPO6/OVVSYNC O O O O O 208, 207 206 to 201 199 195 197 Video clock (27 MHz) Horizontal synchronization Vertical synchronization L L Video data Video data Function Active Polarity 1.3 Audio Input Interface Name IO Pin Number IALRCK IABCK IABD I I I 7 8 9 Left/Right clock Bit clock Bit data Function Active Polarity Data Sheet S15082EJ4V0DS 9 PD61051, 61052 1.4 Audio Input/output Interface After hardware reset, it becomes input. OALRCK, OABCK and OABD connect with 3.3 V VDD through the 10 k pull up resistance. Firmware controls input/output of those pins. Name IO Pin Number OALRCK OABCK OABD AMCLK IO IO IO I 4 5 6 2 Left/Right clock Bit clock Bit data Audio clock Function Active Polarity 1.5 Stream Input Interface Stream input corresponds to MPEG TS/PS stream. When slave mode (MPEG2-TS input with using valid signal), data input is possible to select 8 bits parallel data or serial data mode. When serial data mode, data input to IS0. Active polarity of ISREQ is selected by the port setup register. Active polarity of ISCLK/ISSTB, ISSYNC ISERR and ISVLD are selected by firmware. These are unsettled after the turning on. Name IO Pin Number ISREQ O 55 Stream data request Only parallel interface, this pin is active. After reset, default is active low. ISCLK/ISSTB I 53 Stream data strobe After reset, default is ISCLK. ISCLK/ISSTB I 53 Stream data clock After reset, default is active high edge. ISSYNC I 52 Stream data synchronization After reset, default is active high. ISVLD I 54 Stream data valid After reset, default is active low. IS1/ISERR I 43 Stream error After reset, default is active high. IS1/ISERR IS7 to IS2, IS0 I I 43 51,49, 47 to 44, 42 Stream data input Stream data input Function Active Polarity Remark In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register. 10 Data Sheet S15082EJ4V0DS PD61051, 61052 1.6 Stream Output Interface This interface outputs MPEG TS/PS stream. When in master mode (MPEG2-TS output with using valid signal), data output is possible to select 8bits parallel data or serial data mode. In serial mode, data output from OS0. Active polarity of OSVLD is selected by the port setup register. Active polarity of OSCLK/OSSTB and OSSYNC are selected by firmware. These are unsettled after the turning on. Name IO Pin Number OSREQ OSCLK/OSSTB I O 70 66 Stream data request in slave mode Stream data strobe After reset, default is active high edge. OSCLK/OSSTB O 66 Stream data clock After reset, default is OSSTB. OSSYNC O 67 Stream data synchronization After reset, default is active high. OSVLD/OSRDY O 68 Stream data valid After reset, default is OSRDY. OSVLD/OSRDY O 68 Stream data ready prepared After reset, default is active low. OS7 to OS0/ FA13 to FA6 O 65 to 63, 61, 59 to 56 Stream data output Function Active Polarity L Remark 1.7 In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register. SDRAM Interface Name IO Pin Number Function Active Polarity MA13 to MA0 O 104, 103, 115, 102, 114, 113, 111, 109, 108, 106, 101, 99, 97, 95 MD31 to MD0 IO 93 to 89, 87, 85, 83, 72, 75 to 81, 149, 147 to 143, 141, 139, 127, 129, 131 to 134, 136, 138 MCLK MCKE MCS MRAS MCAS MWE MDQM O O O O O O O 118 116 120 121 123 125 126 Data (Built-in 50 k pull up resistor) Clock Clock enable Chip selection Row address strobe Column address strobe Write enable Data input/output mask enable H L L L L L Address of row/column Data Sheet S15082EJ4V0DS 11 PD61051, 61052 1.8 Host CPU Interface It chooses a parallel bus connection and a serial bus connection by the setting of CMODE2. Name IO Pin Number CMODE2 I 158 Host CPU interface select L: Parallel, H: Serial Function Active Polarity 1.8.1 Parallel bus interface Name IO Pin Number Function Active Polarity CA5 to CA0/ FA5 to FA0 CD7 to CD0/ FD7 to FD0 CWE/CSDI CRE CCS CINT CWAIT/FOE CMODE0/CSCLK I 187, 185 to 181 Address IO 172, 170 to 166, 164, 162 157 160 159 153 161 155 Data I I I O O I Write enable Read enable Chip selection Interrupt Wait Setting of polarity of CWAIT L: Low wait, H: High wait L L L H CMODE1/CSDO I 156 Setting of operation of CWAIT (Built-in 50 k pull up resistor) L: Wait operation.(after ready, pin continues ready) H: Ready operation.(after ready, pin turns to wait) 1.8.2 Serial bus interface When connecting a serial bus, it downloads instruction of internal CPU from instruction ROM. (1) Serial bus interface Name IO Pin Number CMODE0/CSCLK I 155 SPI serial interface clock Fix CSCLK to high level during CCS is disable (high level). CWE/CSDI CMODE1/CSDO I O 157 156 SPI serial interface data input SPI serial interface data output (Built-in 50 k pull up resistor) CCS CINT I O 159 153 Chip selection Interrupt L H Function Active Polarity 12 Data Sheet S15082EJ4V0DS PD61051, 61052 (2) Instruction ROM interface Name IO Pin Number Function Active Polarity CA5 to CA0/ FA5 to FA0 OS7 to OS0/ FA13 to FA6 OVOUT5 to OVOUT0/ FA19 to FA14 CD7 to CD0/ FD7 to FD0 CWAIT/FOE O I 172, 170 to 166, 164, 162 161 Output enable L Data O O 65 to 63, 61, 59 to 56 206 to 201 Address Address O 187, 185 to 181 Address 1.9 Clock, Reset Name IO Pin Number Function H Active Polarity SCLK STCLK PSTOP I I I 28 34 29 System clock System time clock Internal PLL operation control L: Normal, H: Internal PLL stop PWM RESET O I 40 151 PWM output Reset L 1.10 N-Wire IE Port for firmware of Internal CPU evaluation When not connecting an in-circuit emulator, take countermeasures against noise by pulling up the NDI pin to avoid the pin becoming low level. Name IO Pin Number Function Active Polarity NMOD I 178 Pin used when connecting IE Pull up when connecting IE NCLK NRST NDI NDO I I I O 174 176 179 180 Serial clock N-wire reset Data input Data output L H Data Sheet S15082EJ4V0DS 13 PD61051, 61052 1.11 GPIO GPIO becomes input after hardware reset by the RESET pin and ALL RESET by the reset register. GPIO connect with 3.3 V VDD through the 10 k pull up resistance. Name IO Pin Number GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPO5/OVHSYNC GPO6/OVVSYNC IO IO IO IO IO O O 189 190 191 192 193 195 197 Firmware use pin Firmware use pin Firmware use pin Firmware use pin Firmware use pin Firmware use pin Firmware use pin Function Active Polarity 1.12 Power Supply Name IO Pin Number Function Active Polarity VDD3 39, 69, 86, 98, 110, 122, 135, 148, 171, 194 VDD2 1, 13, 24, 36, 48, 60, 71, 82, 94, 105, 117, 128, 140, 152, 163, 175, 186, 198 GND 3, 10, 15, 26, 27, 35, 37, 38, 41, 50, 62, 73, 74, 84, 88, 96, 100, 107, 112, 119, 124, 130, 137, 142, 150, 154, 165, 173, 177, 188, 196, 200 PVDD2 PGND 30, 32 31, 33 2.5 V power supply for PLL GND for PLL 2.5 V power supply for the internal circuit 3.3 V power supply for interface GND 14 Data Sheet S15082EJ4V0DS PD61051, 61052 1.13 Recommended Connections of Unused Pins Connect unused pins as follows. Name IVIN7 to IVIN0 IVCLK IVHSYNC IVVSYNC IVFLD OVOUT7, OVOUT6 OVOUT5 to OVOUT0/FA19 to FA14 OVCLK IALRCK IABCK IABD OALRCK OABCK OABD AMCLK ISREQ ISCLK/ISSTB ISSYNC ISVLD IS7 to IS0 OSREQ OSSYNC CA5 to CA0/FA5 to FA0 CD7 to CD0/FD7 to FD0 CRE CINT CWAIT/FOE PWM NMOD NCLK NRST NDI NDO GPIO4 to GPIO0 GPO5/OVHSYNC GPO6/OVVSYNC IO I I I I I O O O I I I IO IO IO I O I I I I I O IO IO I O O O I I I I O IO O O GND GND GND GND GND Open Open Open GND GND GND Pull up with 10 k resistor Pull up with 10 k resistor Pull up with 10 k resistor GND Open GND GND GND GND GND Open Open Pull up with 10 k resistor GND Open Open Open Pull up with 4.7 k resistor Pull up with 4.7 k resistor Pull down with 50 k resistor Pull up with 4.7 k resistor Pull up with 4.7 k resistor Pull up with 10 k resistor Open Open Connection Data Sheet S15082EJ4V0DS 15 PD61051, 61052 2. FEATURE OVERVIEW The functions and I/O interfaces are set using firmware. Supported functions differ depending on firmware. 2.1 Video This LSI can do flexible encoding and transcoding by using the firmware control of internal CPU and an exclusive use circuit. NTSC/PAL video format, which is possible of the encoding is as in Table 2-1. NTSC/PAL video format of the transcoding is under 720 dots by 480/576 line/frame. Table 2-1. Video Format MPEG2 Yes Yes Yes Yes Yes Yes MPEG1 No No No No No Yes Video format 720 dots by 480/576 line/frame 704 dots by 480/576 line/frame 544 dots by 480/576 line/frame 480 dots by 480/576 line/frame 352 dots by 480/576 line/frame 352 dots by 240/288 line/frame 2.1.1 Encoding It encodes the video that was converted from the 4:2:2 format into the 4:2:0 format in the video input/output unit with MPEG2 standard MP@ML, SP@ML and the MPEG1 standard. It is encoding in variable bit rate (single path VBR encoding) or constant bit rate (CBR). The pre analysis supports high quality picture encoding. Encode supports frame structure. * Using the following, only 64 Mbits SDRAM is needed. Encoding with locally decoding and/or time base corrector (TBC) PAL encoding * DVD encoding needs equal to 128 Mbits SDRAM area. * The motion estimation size P picture: 128 dots (H) by 64 lines (V) B picture: 96 dots (H) by 48 lines (V), 64 dots (H) by 32 lines (V) * I/P picture period in MP@ML : M 3 * Dual prime estimate, only at the time of M = 1. 2.1.2 Transcoding It transcodes the stream of MPEG2 standard MP@ML based. It is possible for the bit rate conversion. 16 Data Sheet S15082EJ4V0DS PD61051, 61052 2.1.3 Input/output processing (1) Video input The video input format is ITU-R BT.656 (8-bit Y/Cb/Cr the 4:2:2 format) and 8-bit Y/Cb/Cr which deals with the 4:2:0 format. The horizontal synchronization signal, the vertical synchronization signal and the field index can be used without using SAV and EAV. In this case, IVFLD can be used by taking with IVVSYNC or it judges a field judgment in the polarity of IVHSYNC behind the falling edge two clock of IVVSYNC. It judges that an odd field is 'H' and an even field is 'L'. IVVSYNC and IVHSYNC need the high / low period more than 3 IVCLK. The video-input unit watches over the synchronization signals and detects synchronous error. (2) Picture size conversion filter For adapting to the bit rate of the stream, the picture size of the encoding can be changed. In addition, picture size changed with the external filter to the 4:2:0 format can be inputted directly, too. Table 2-2. Input Video Data Arrangement Format 4:2:2 4:2:0 Line Odd/even lines Odd lines Even lines Data arrangement Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, ... Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, ... (-), Y0, (-), Y1, (-), Y2, (-), Y3, (-), Y4, (-), Y5, ... (3) Time base corrector (TBC) It has a frame-type TBC. It is possible to make stable encoding of the channel changing and the nonstandard video signal such as VTR. When using TBC, it needs over 64 Mbits SDRAM. The following video signals can be corrected. Table 2-3. Correctable Video Signals Horizontal Sync NTSC PAL 1626 to 1806 IVCLK/H 1628 to 1828 IVCLK/H Vertical Sync 246 to 278 H/V 294 to 330 H/V Remark IVCLK: 27 MHz (4) Noise reduction Respectively the noise reduction of the luminance signal and the color signal can be set three levels (5) Slicer Slicer decodes the luminance signal to the vertical blanking data. It detects VBID, Closed Caption, and Wide Screen Signal. The host CPU can read, and stop encoding and re-write the copy control information in VBID and the Wide Screen Signal, on the host CPU interface. Data Sheet S15082EJ4V0DS 17 PD61051, 61052 Table 2-4. Slicer TV method NTSC VBID Closed caption PAL Wide screen signal VBI data Detection line 20, 283 21, 284 23 (336) (6) Video output It converts an input video or a local-decoded video into picture size of 720 dots by 480/576 line and outputs with the ITU-R BT.656 format. Horizontal and vertical synchronization signals are switched from GPO. Field detection is easy due to vertical synchronization signal delays 4VCLK since horizontal synchronization signal. Figure 2-1. Video Output (a) Odd Field OVVSYNC (NTSC) OVVSYNC (PAL) OVHSYNC 3H 2.5H OVCLK OVVSYNC 4OVCLK OVHSYNC (b) Even Field OVVSYNC (NTSC) OVVSYNC (PAL) OVHSYNC H/2+4 OVCLK 3H 2.5H 18 Data Sheet S15082EJ4V0DS PD61051, 61052 2.2 Audio This LSI encodes the MPEG audio encoding and transcode with the internal DSP. 2.2.1 Encoding It encodes MPEG1 audio layer 2 or Dolby Digital Consumer Encoder (only the PD61052). In addition, it is possible to bypass internal audio encode DSP, when the audio elementary stream is encoded by an external audio encoder are inputted. 2.2.2 Transcoding (DEMUX, MUX) It is possible to multiplex two de-multiplexed audio streams. It analyzes MPEG1 audio stream, and extracts the information to multiplex and notify to the host CPU. 2.2.3 Input/output processing Two PCM audio signals can be inputted to the audio input interface and the audio input-output interface. When inputting two audio signals, an audio signal is encoded, and another one bypasses the audio encoding DSP, and transfers to the multiplexer. When inputting an audio elementary stream that has been encoded by the external audio encoder and PCM audio, it can multiplex two audio elementary streams. The PCM audio or the audio elementary stream can be outputted from the audio input-output interface. The audio clock (AMCLK) types the clock by which a phase was locked up STC clock (STCLK). Table 2-4. Audio Input/output Item Data length Sampling frequency Justification of transfer Input/output format 16 bits, 20 bits, 24 bits 32 kHz, 44.1 kHz, 48 kHz MSB first I S Compatible/Left justified/Right justified Format PCM Audio, IEC60958 based 2 Data Sheet S15082EJ4V0DS 19 PD61051, 61052 Figure 2-2. Audio Input (a) MSB First Right Justified Mode IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) Lch Rch Don't care MSB LSB Don't care MSB LSB Audio data 16/32 IABCK (OABCK) (b) MSB First Left Justified Mode IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) Lch Rch MSB LSB MSB LSB Audio data 16/32 IABCK (OABCK) (c) I2S Mode IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) Lch Rch MSB LSB MSB LSB Audio data 32 IABCK (OABCK) 20 Data Sheet S15082EJ4V0DS PD61051, 61052 Figure 2-3. Audio Output (a) MSB First Right Justified Mode OALRCK OABCK OABD MSB Lch Rch MSB LSB MSB MSB LSB Audio data 16/32 OABCK (b) MSB First Left Justified Mode OALRCK OABCK OABD MSB Audio data Lch Rch LSB MSB LSB 16/32 OABCK (c) I2S Mode OALRCK OABCK OABD MSB Lch Rch LSB MSB LSB Audio data 32 OABCK Data Sheet S15082EJ4V0DS 21 PD61051, 61052 2.3 MPEG System Processing This LSI multiplexes and/or de-multiplexes Audio and video streams based on MPEG2-TS/PS and MPEG1. By combining the multiplexer and de-multiplexer, it does the transcode which is accompanied by MPEG2-TSMPEG2 PS conversion. 2.3.1 System time clock (1) Encoding system When the encoding system operates, it uses the clock input to STCLK that is generated with the 27 MHz oscillator. Audio master clock is made with 27 MHz of STCLK, and then Audio synchronizes to STC. Figure 2-4. System Time Clock Input (Encoding System) IVIN7 to IVIN0 Video Decoder 27 MHz IVCLK Audio in Audio ADC AMCLK XTAL 27 MHz PLL 27 MHz SCLK 27 MHz STCLK PWM PD61051/61052 22 Data Sheet S15082EJ4V0DS PD61051, 61052 (2) Encoding and Transcoding system It can output the signal, which generates the pulse wide modulation (PWM) with comparing PCR/SCR of the stream and system time clock value, for making the reference clock of the system. Figure 2-5. System Time Clock Input (Encoding and Transcoding System) IS OS IVIN7 to IVIN0 Video Decoder 27 MHz IVCLK Audio in Audio ADC AMCLK 27 MHz XTAL PLL VCO 27 MHz SCLK 27 MHz STCLK Filter PWM PD61051/61052 2.3.2 Multiplex It stamps SCR, PCR, DTS and PTS after multiplexing streams that are from the video encoder and the audio encoder based on MPEG2-TS/PS. Partial TS can be made by forming SIT packet from PSI and SI data of base on DVB. It is possible to multiplex the packet that inputted from the host CPU interface. 2.3.3 De-multiplex (1) MPEG2-TS Using the PID filter corresponding to 16 PIDs, It separates MPEG2-TS to one video stream, two audio streams, and two user data streams. Internal CPU extracts section data in PSI and SI of base on DVB. (2) MPEG2-PS With the stream ID filter, it separates MPEG2-PS to one video stream, one audio stream, and two user data streams. Data Sheet S15082EJ4V0DS 23 PD61051, 61052 (3) VBI data The user data stream, the wide screen signal, the closed caption, VBID and format of the video and the audio can be read from the host CPU interface. 2.3.4 Transcode The transcode is a combined multiplexer and de-multiplexer. MPEG2-TS/PS separates into a video stream, two audio streams, and two user data streams. The video stream and the audio stream are multiplexed to MPEG2-TS/PS after transcode on the elementary. PCR, SCR, PTS and DTS are corrected when multiplexing. In the transcode of MPEG2-TS, it can generate partial TS using the data detected by the PID filter and the section filter. Figure 2-6. Transcode MPEG2 Video Bit Rate Conversion Stream MPEG2-TS/PS De-multiplexer MPEG2-TS/PS Multiplexer Stream Audio ES Stream Buffer Audio ES Stream Buffer The change of the MPEG system layer is shown below. MPEG2-TS MPEG2-TS MPEG2-TS MPEG2-PS MPEG2-PS MPEG2-TS MPEG2-PS MPEG2-PS MPEG1 MPEG1 24 Data Sheet S15082EJ4V0DS PD61051, 61052 2.4 Stream Interface When it inputs MPEG2-TS, it is able to connect parallel data or serial data with the PD61051/61052. When it inputs MPEG2-PS, it should connect parallel data with the PD61051/61052. 2.4.1 Parallel steam data interface When parallel interface, the This LSI connects to external device by the master mode or the slave mode. and transcode is limited to 15 Mbps on MPEG MP@ML. (1) Stream Input It is possible to receive 4 bytes data after invalid of ISREQ of the stream input. Remark ISSTB and ISCLK are identical pins. Figure 2-7. Parallel Stream Receiving Mode (1/2) (a) Example for Receiving of MPEG2-TS 1 packet (188 bytes) ISVLD maximum stream input rate is 100 Mbps, the maximum stream output rate is 30 Mbps. The stream of MPEG encoding ISCLK IS7 to IS0 No received data 1st Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data No received data ISSYNC Release in a TS packet ISCLK shall be under 13.5 MHz. Data Sheet S15082EJ4V0DS 25 PD61051, 61052 Figure 2-7. Parallel Stream Receiving Mode (2/2) (b) Example of Receiving MPEG2-PS, ES with Valid and Clock ISREQ It is possible to receive till 4 bytes ISVLD ISCLK IS7 to IS0 No received data Valid data Valid data Valid data Valid data Valid data Valid data No received data No received data Valid data Valid data No No recei- received ved data data ISSYNC Don't care (c) Example of Receiving MPEG2-PS, MPEG2-ES with a Strobe ISREQ It is possible to receive till 4 bytes ISSTB IS7 to IS0 No received data Valid data Valid data Valid data Valid data Valid data Valid data No received data No received data Valid data Valid data No No recei- received ved data data ISSYNC Don't care (2) Stream output There are two modes: valid operation master mode and strobe operation byte transfer mode. The appropriate transfer mode for the system can be selected by setting the two stream output mode and transfer rate. Remark OSSTB and OSRDY are the same pins as OSCLK and OSVLD, respectively. Operation can be selected using combinations of OSSTB and OSRDY or OSCLK and OSVLD. 26 Data Sheet S15082EJ4V0DS PD61051, 61052 (a) Master Mode Valid This is the MPEG2-TS dedicated output mode. The period of OSCLK can be selected from n times 37 ns (1/27 MHz) (3 n 255, n is an integer). If using local decode or input video display, the period is 4 n 255 (n is an integer). Figure 2-8. Parallel Stream Transmission Mode ; Transmission of MPEG2-TS (Packet Length is 188 Bytes) (a) Master Mode, Valid 1 packet (188 bytes) OSVLD OSCLK OS7 to OS0 Invalid 1st Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Invalid Invalid OSSYNC (b) The Transfer Condition from Reset RESET OSVLD Unsettled OSCLK Unsettled OS7 to OS0 Unsettled (Data does not change) OSSYNC Unsettled The setting of an interface mode The stream preparation completion Data Sheet S15082EJ4V0DS 27 PD61051, 61052 (b) Bytes Transfer Mode, Strobe In byte transfer mode, the transfer rate is determined by the handshake of OSREQ and OSSTB. Figure 2-9. Parallel Stream Transmission Mode (Transmission of MPEG2-PS, MPEG2-ES) (a) Example for Transmission of Strobe Mode One Byte Transfer OSRDY OSREQ OSSTB OS7 to OS0 OSSYNC (b) The Transfer Condition from Reset RESET OSRDY Unsettiled OSREQ OSSTB Unsettiled OS7 to OS0 Unsettled (Data does not change) OSSYNC Unsettiled The setting of an interface mode The stream preparation completion 28 Data Sheet S15082EJ4V0DS PD61051, 61052 2.4.2 Serial stream data interface This LSI is able to input a serial stream. Bit rate of serial input is limited less than parallel interface. Serial Stream Interface can transfer only MPEG2-TS stream. Maximum bit rate of stream input is less then 64 Mbps. Bit rate of stream out is 27 Mbps. Additionally, encoding and transcoding bit rate is limited to 15 Mbps on MPEG2 MP@ML. (1) Stream input ISCLK is input by less than 64 MHz clock. Data is MSB first. ISSYNC should active while first byte each packet. If packet error occurred, ISERR should active from ISSYNC of the packet. ISVLD should valid while each byte. ISVLD shall invalid while 8 bits between each packets. Data Sheet S15082EJ4V0DS 29 PD61051, 61052 Figure 2-10. Serial Stream Input First Byte of TS packet One packet More than 8 ISCLK ISVLD ISCLK IS0 MSB Bit6 Bit1 Bit0 MSB Bit0 Invalid MSB ISSYNC IS1/ISERR ISVLD ISCLK MSB IS0 LSB MSB LSB MSB LSB MSB ISSYNC IS1/ISERR "L" Remark Example for ISVLD, ISSYNC, ISERR active high, ISCLK active high edge 30 Data Sheet S15082EJ4V0DS PD61051, 61052 (2) Stream Output OSCLK is fixed 27 MHz OSSYNC active at first byte in each packet. OSVLD is active of 1 packet continuously. Data is the MSB first outputs. ISSYNC becomes active among 1 byte at the head of the packet. Figure 2-11. Serial Stream Output First Byte of TS packet One packet More than 8 ISCLK OSVLD OSCLK OS0 MSB Bit6 Bit1 Bit0 MSB Bit0 Invalid MSB OSSYNC OSVLD OSCLK MSB OS0 LSB MSB LSB MSB LSB MSB OSSYNC Remark Example for OSVLD, OSSYNC, OSERR active high Data Sheet S15082EJ4V0DS 31 PD61051, 61052 2.5 Host CPU Interface The connection of the host CPU can select the eight bits parallel data interface and serial interface (SPI). Internal CPU sends and receives command status through the System Interface Register, which is in the host CPU interface unit. In addition, to control an internal DMA controller through the system interface register, it loads an instruction for internal CPU to the instruction RAM and the transfer of the large-volume data can be sent to the data area on SDRAM. Figure 2-12. Host CPU Interface Instruction RAM of Internal CPU Host CPU System Interface Register DMA Controller Internal CPU SDRAM Interface SDRAM PD61051/61052 The following describes loading of internal CPU instruction. (1) Parallel interface When parallel interface is selected, host interface has 6-bit address, 8-bit data bus and control ports. CWAIT is selected with CMODE1 to wait on ready signal mode, CMODE1 selects active polarity of CWAIT. (2) Serial interface The PD61051/61052 communicates with the host CPU using the SPI (serial peripheral interface) serial bus. The host CPU becomes a bus master. The low edge of the chip selection is communication beginning. Its high edge is communication ending. An address and the reading / writing mode are shown at the first byte after the chip selection becomes low. It is the MSB first of six bits of addresses, eight bits of data. Fix CSCLK to high level during CCS is disabled (high level). The PD61051/61052 becomes a master and downloads the instruction of the internal CPU from external ROM. CSCLK: CSDI: CSDO: CCS: The serial clock The data input The data output The chip selection 32 Data Sheet S15082EJ4V0DS PD61051, 61052 Figure 2-13. Serial Interface [Data Write] CCS CSCLK CSDI CSDO xx A5 A4 A3 A2 A1 A0 W x xx D7 D6 D5 D4 D3 D2 D1 D0 x [Data Read] CCS CSCLK CSDI CSDO xx A5 A4 A3 A2 A1 A0 xx R x x x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 2.6 SDRAM Interface External memory is SDRAM. It is possible to use the following. Table 2-6. Use Memory Memory 16 Mbit SDRAM 64 Mbit SDRAM 64 Mbit SDRAM 128 Mbit SDRAM 128 Mbit SDRAM Data bus width 16 bits 32 bits 16 bits 16 bits 32 bits 2 1 2 2 1 Quantity Use memory capacity 32 Mbits 64 Mbits 128 Mbits 128 Mbits 128 Mbits The PD61051/61052 preserves the part of the parameter that is necessary to generate the stream, entry video image, a video stream, an audio stream, a stream header, user data, and the instruction of the firmware at this memory. This system uses only CAS latency = 3, burst length = 4. When encode using time base corrector and/or displays local decoding picture, it needs equal to or more than 64 Mbits SDRAM. When PAL encoding, it needs equal to or more than 64 Mbit SDRAM. When transcoding, it needs equal to or more than 64 Mbit SDRAM. Data Sheet S15082EJ4V0DS 33 PD61051, 61052 2.7 Memory Connection Diagram Each memory connection is as follows. Figure 2-14. Memory Connection Diagram (1/2) (a) 16 Mbit SDRAM by 2 A11 1 Mbitsx16 SDRAM A10 to A0 D15 to D0 PD61051/61052 MA13 MA12 MA11 MA10 to MA0 MD31 to MD16 MD15 to MD0 A11 1 Mbitsx16 SDRAM A10 to A0 D15 to D0 Bank A: SDRAM address = 0x xxxx xxxx xxxxB Bank B: SDRAM address = 1x xxxx xxxx xxxxB (b) 64 Mbit SDRAM by 1 PD61051/61052 MA13 MA12 MA11 MA10 to MA0 MD31 to MD16 MD15 to MD0 A12 A11 A10 to A0 2 Mbitsx32 SDRAM D31 to D16 D15 to D0 Bank A: SDRAM address = 00 xxxx xxxx xxxxB Bank B: SDRAM address = 10 xxxx xxxx xxxxB Bank C: SDRAM address = 01 xxxx xxxx xxxxB Bank D: SDRAM address = 11 xxxx xxxx xxxxB 34 Data Sheet S15082EJ4V0DS PD61051, 61052 Figure 2-14. Memory Connection Diagram (2/2) (c) 64 Mbit SDRAM by 2 or 128 Mbit SDRAM by 2 MA13 4 Mbitsx16 SDRAM MA12 MA11 MA10 to MA0 D15 to D0 PD61051/61052 MA13 MA12 MA11 MA10 to MA0 MD31 to MD16 MD15 to MD0 A13 4 Mbitsx16 SDRAM A12 A11 A10 to A0 D15 to D0 Bank A: SDRAM address = 00 xxxx xxxx xxxxB Bank B: SDRAM address = 10 xxxx xxxx xxxxB Bank C: SDRAM address = 01 xxxx xxxx xxxxB Bank D: SDRAM address = 11 xxxx xxxx xxxxB Data Sheet S15082EJ4V0DS 35 PD61051, 61052 2.8 Memory Map Firmware sets memory map such as video image area and usable work area. Firmware cabinet (temporal buffered area) is the area which firmware does not use. Video Image area size is changed NTSC or PAL. Each area are changed by the firmware. Figure 2-15. Memory Map (1/2) (a) 16 Mbit SDRAM by 2 Firmware Firmware Firmware 00000H Bank A Video Stream Bank B Video Stream Audio Stream User Data 0 Video Image Area Header 7FFFFH (b) Example for 64 Mbit SDRAM by 1 Firmware Firmware Firmware Bank A 00000H Video Stream 0 Bank B Video Stream 0 Bank C Video Stream 1 Audio stream 1 Bank D Video Stream 1 00000H User data 1 Unused Audio stream 0 User data 0 Video Image Area Video Image Area Firmware Header Instruction Pool Instruction Pool Firmware 7FFFFH Usable Work Area Usable Work Area 7FFFFH 36 Data Sheet S15082EJ4V0DS PD61051, 61052 Figure 2-15. Memory Map (2/2) (c) Example for 64 Mbit SDRAM by 2 or 128 Mbit SDRAM by 2 Bank A Firmware Bank B Video Stream Bank C Unused Bank D Unused 00000H 00000H Video Stream Unused Header Video Image Area Video Image Area Firmware Unused Unused 80000H Video Stream Instruction Pool Firmware Video Stream Instruction Pool Audio Stream Audio Stream Firmware Usable Work Area Usable Work Area User data 0 User data 1 FFFFFH FFFFFH Data Sheet S15082EJ4V0DS 37 PD61051, 61052 3. SYSTEM INTERFACE REGISTER This LSI corresponds to the various operation modes in exchange instruction of internal CPU from SDRAM to instruction RAM (iRAM). This has 64 byte Registers. They are defined to common registers, interrupt registers and interrupt mask registers. When there is access in the same address from both of the internal CPU and the host CPU, the later data is left at the register. Also, when the writing occurs to the same address at the same time about the common register, the data of the host CPU is left at the register Figure 3-1. System Interface Register Instruction RAM of Internal CPU System Interface Register Internal CPU Host CPU DMA Controller SDRAM Interface SDRAM PD61051/61052 38 Data Sheet S15082EJ4V0DS PD61051, 61052 3.1 Register Mapping (General Mapping) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W SDW SA19 to SA16 SA15 to SA8 SA7 to SA0 DA16 DA15 to DA8 DA7 to DA0 TC18 to TC16 TC15 to TC8 TC7 to TC0 iCPU-INT DMAERR-M 2CH 2DH 2EH 2FH 30H Defined by firmware Defined by firmware Defined by firmware Defined by firmware DMA-ERR DMA-RDY DMADONE 31H 32H 33H 34H 35H 36H 37H to 3DH 3EH NBR ALL RESET 3FH TD7 to TD0 R/W Transfer data R/W Reset Defined by firmware Defined by firmware Defined by firmware Defined by firmware iROM2 to iROM0 ISREQ OSVLD R/W R/W R/W R/W R/W R/W Interrupt1 Interrupt2 Interrupt3 Interrupt4 Mask ROM cycle Port setup DMARDY-M DMADONE-M R/W R/W R/W R/W R/W Interrupt mask1 Interrupt mask2 Interrupt mask3 Interrupt mask4 Interrupt0 SDR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Download mode Source address Source address Source address Destination address Destination address Destination address Transfer data count Transfer data count Transfer data count Int. to internal CPU Interrupt mask0 Address 00H to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH Defined by firmware SI SSD SDI MSD MI Data Sheet S15082EJ4V0DS 39 PD61051, 61052 3.2 3.2.1 Address 00H to 1FH Register Functions Common register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W Defined by firmware Each firmware defines these registers. These registers are used to communicate with host CPU and internal CPU. For the details of the register, refer to the application notebook. The reset of the RESET pin or ALL RESET of the reset register initializes addresses 00H and 01H addresses to 0H. The original value of the other register is unsettled. It keeps a setting value before reset. 3.2.2 Data transfer register These registers are defined data transfer such as host CPU SDRAM, SDRAM host CPU, host CPU iRAM of internal CPU, SDRAM iRAM of internal CPU and instruction ROM iRAM of internal CPU. The host CPU transfers with SDRAM via had a transfer buffer of 128 bytes on this LSI. The transfer with the instruction RAM becomes 4 bytes. A transfer error occurs if the transfer mode register, source address register, destination address register, or transfer counter register is changed before releasing the transfer mode register following transfer completion after setting the transfer mode register and starting the transfer. When transferring data as follows: host CPU instruction RAM of internal CPU, host CPU SDRAM, SDRAM instruction RAM of internal CPU, instruction ROM SDRAM, instruction ROM instruction RAM of internal CPU, execute a software reset of the internal CPU (address 3EH 02H) before transfer and release the reset after transfer. 40 Data Sheet S15082EJ4V0DS PD61051, 61052 (1) Data transfer register Address 20H Bit7 SI Bit6 SSD Bit5 SDI Bit4 MSD Bit3 MI Bit2 Bit1 SDW Bit0 SDR R/W R/W Download mode Bit 7 SI Field Function Host CPUinstruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer Note Initial value 0 6 SSD Host CPUSDRAM 0: Releasing of transfer, 1: Transfer Note 0 5 SDI SDRAMinstruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer Note 0 4 MSD Instruction ROMSDRAM 0: Releasing of transfer, 1: Transfer Note 0 3 MI Instruction ROMinstruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer Note 0 2 1 SDW Reserved (set only 0) Host CPUSDRAM 0: Releasing of transfer,1: Transfer 0 0 0 SDR SDRAMhost CPU 0: Releasing of transfer, 1: Transfer 0 Note Set internal CPU reset (with Register 3EH02H) More than one bit cannot be set to 1 at the same time. It becomes a transfer error when writing at the transfer mode register while transferring. When canceling a transfer while transferring, it stops a transfer. At this time, the data in the transfer buffer becomes invalid. The transfer of SDR with once is to a maximum of 128 bytes. If host CPU stops the transfer, host CPU should operate transfer error handling. Data Sheet S15082EJ4V0DS 41 PD61051, 61052 (2) Source address register Address 21H 22H 23H SA15 to SA8 SA7 to SA0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W Source address Source address Source address SA19 to SA16 It sets the address of the data to transfer. It becomes effective in case of transfer from SDRAM or instruction ROM. Until it releases a transfer mode after setting a transfer mode register, it isn't possible to change. The transfer error occurs when rewriting this register before releasing a transfer mode. The relation with the address of SDRAM, external instruction ROM is shown in Figure 3-2 and 3-3. The addressing of SDRAM becomes a 32 address by 4-word unit (128 bytes). The relation with the SDRAM bank and address is shown in Table 3-1. Figure 3-2. Relation of Source Address and SDRAM Address Host CPU interface register 21H to 23H SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 A15 A14 A13 A12 A11 A10 A9 A8 0000 A21 A20 A19 A18 A17 A16 SDRAM address A7 A6 A5 Bank select Figure 3-3. Relation of Source Address and External Instruction ROM Address Host CPU interface register 21H to 23H SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 0000 Extemal instruction ROM address FA19 FA18 FA17 FA16 FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 Table 3-1. Relation of SDRAM Bank and Address Memory 16 Mbit SDRAM by 2 16 Mbit SDRAM by 1 64 Mbit SDRAM by 2 128 Mbit SDRAM by 1 128 Mbit SDRAM by 2 128 Mbit SDRAM by 1 000000H to 0FFFFFH 200000H to 2FFFFFH 100000H to 1FFFFFH 300000H to 3FFFFFH Bank A 000000H to 07FFFFH 000000H to 07FFFFH 000000H to 0FFFFFH Bank B 200000H to 27FFFFH 200000H to 27FFFFH 200000H to 2FFFFFH Bank C 100000H to 17FFFFH 100000H to 1FFFFFH Bank D 300000H to 37FFFFH 300000H to 3FFFFFH 42 Data Sheet S15082EJ4V0DS FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 00000 The PD61051/61052 adds 0 automatically PD61051, 61052 (3) Destination address register Address 24H 25H 26H DA15 to DA8 DA7 to DA0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DA16 R/W R/W R/W R/W Destination address Destination address Destination address It sets Destination address. It becomes effective in case of transfer to SDRAM or instruction RAM of internal CPU. It isn't possible to change until it cancels a transfer mode after setting a transfer mode register. It becomes a transfer error when rewriting before canceling a transfer mode. The relation of the address of SDRAM and instruction RAM of internal CPU is as in Figure 3-4 and 3-5. The addressing of SDRAM becomes a 32 address by 4-word unit (128 bytes). Figure 3-4. Relation of Destination Address and SDRAM Address Host CPU interface register 24H to 26H DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 A15 A14 A13 A12 A11 A10 A9 A8 0000000 A21 A20 A19 A18 A17 A16 SDRAM address A7 A6 A5 Bank select Figure 3-5. Relation of Destination Address and Instruction ROM Address of Internal CPU Host CPU interface register 24H to 26H DA16 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 0000000 Instruction RAM address of intemal CPU A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 00000 The PD61051/61052 adds 0 automatically Data Sheet S15082EJ4V0DS 43 PD61051, 61052 (4) Transfer data counter register Address 27H 28H 29H TC15 to TC8 TC7 to TC0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 TC18 to TC16 Bit0 R/W R/W R/W R/W Transfer data count Transfer data count Transfer data count It sets the transfer data number of the bytes. In case of transfer between host CPU and SDRAM, it sets the number of the transfer bytes by 4 bytes unit. In case of transfer from instructions ROM, SDRAM host CPU to the instruction RAM of internal CPU, it sets the number of the transfer bytes /4 by the 4 byte unit. (5) Transfer data register Address 3FH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W Transfer data TD7 to TD0 This register is transfer data window. Figure 3-6. SDRAM Write SDRAM address = DA16 to DA0x128 Byte3 Byte7 Byte11 Byte15 Byte19 Byte2 Byte6 Byte10 Byte14 Byte18 Byte1 Byte5 Byte9 Byte13 Byte17 Byte0 Byte4 Byte8 Byte12 Byte16 SDRAM address = DA16 to DA0x128+5 SDRAM Transfer buffer (128 bytes) Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Lower byte first TD7 to TD0 Host CPU write 44 Data Sheet S15082EJ4V0DS PD61051, 61052 SDRAM read <1> Interrupt mask Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer. <2> Set source address Host CPU sets the address of SDRAM to the source address register (21H to 23H) of the PD61051/61052. <3> Set the number (equal to or less than 128 bytes) of the data to read by 4 bytes unit Host CPU sets the data number of the bytes to the transfer data counter register (27H to 29H) of the PD61051/61052. <4> Set the transfer of SDRAM host CPU. Host CPU sets 01H to the transfer mode register (20H) of the PD61051/61052. <5> CINT interrupt (Interrupt pin) <6> Confirms that the interrupt factor and clear interrupt factor Host CPU confirms that the interrupt register 0 (30H) of the PD61051/61052 becomes 02H or 01H and clears writing a same value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the PD61051/61052. <7> Data read Host CPU reads data from the number of times with the set number of bytes, the transfer data register (3FH) of the PD61051/61052. <8> CINT interrupt (Interrupt pin) <9> Confirm the interrupt factor Host CPU confirms that the interrupt register 0 (30H) of the PD61051/61052 becomes 01H. (It clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the PD61051/61052.) <10> Release of SDRAM host CPU mode Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the PD61051/61052 after setting 00H to the transfer mode register (20H) of the PD61051/61052. <11> Release of interrupt mask It releases the limitation on interrupt which set by <1>. Data Sheet S15082EJ4V0DS 45 PD61051, 61052 SDRAM write <1> Interrupt mask Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer. <2> Set destination address Host CPU sets the address of SDRAM to the destination address register (24H to 26H) of the PD61051/61052. <3> Set the number of the data to write by a 4 byte unit Host CPU sets the data number of the bytes by 4 bytes unit to the transfer data counter register (27H to 29H) of the PD61051/61052. <4> Set the transfer of host CPU SDRAM Host CPU sets 02H to the transfer mode register (20H) of the PD61051/61052. <5> Data write Host CPU writes data to the transfer data register (3FH) of the PD61051/61052 at times with more few 128 bytes or transfer data count register setting value. <6> CINT interrupt (Interrupt pin) <7> Confirm the interrupt factor When the number of the transfer data is less then 128 bytes, host CPU confirms that the interrupt register 0 (30H) of the PD61051/61052 becomes 01H, and go to <9>. <8> Confirm that next data transfer prepare completed Host CPU confirms that the interrupt register 0 (30H) of the PD61051/61052 becomes 02H or 01H and clears a writing sane value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the PD61051/61052. Return to <5> and next data write. <9> Release of SDRAM host CPU Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the PD61051/61052 after setting 00H to the transfer mode register (20H) of the PD61051/61052. <10> Release of interrupt mask It releases the limitation on interrupt which is set by <1>. <11> In the case of an interrupt to internal CPU, it is necessary Host CPU sets a data bank number and the number of the bytes to the address that defined with the firmware. It sets 01H to the 2AH address of the PD61051/61052 and it notifies an interrupt to internal CPU. 46 Data Sheet S15082EJ4V0DS PD61051, 61052 3.2.3 Address 2AH Internal CPU interrupt register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 iCPU-INT R/W R/W Int. to internal CPU Host CPU set interrupt to internal CPU. Internal CPU clears this bit after interrupt operation. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. 3.2.4 Address 2BH Interrupt mask register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W Interrupt mask0 DMA-ERR DMA-RDY DMA-DON -M -M E-M 2CH 2DH 2EH 2FH Defined by firmware Defined by firmware Defined by firmware Defined by firmware R/W R/W R/W R/W Interrupt mask1 Interrupt mask2 Interrupt mask3 Interrupt mask4 These registers are interrupt masks for next interrupt. Interrupt mask can be set bit by bit. When setting an interrupt mask, CINT does not become high even if the interrupt register becomes 1. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. 3.2.5 Address 30H Download interrupt register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W Interrupt0 DMA-ERR DMA-RDY DMA-DON E It is set for 1 when the interrupt factor occurs. The interrupt bit clears when host CPU writes to this register after the interrupt processing. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Clear processing continues until interrupt registers is cleared. Bit 7 to 3 2 Field Reserved (set 0) DMA-ERR Data transfer error 0: Normal, 1: Error Function Initial value 0 1 DMA-RDY Data transfer prepared 0: Normal, 1: Transfer 0 0 DMA-DONE Data transfer ended 0: Normal, 1: Transfer ended 0 It outputs DMA-RDY or DMA-DONE every 128-byte transfer. DMA-DONE is output when the transfer ends. Data Sheet S15082EJ4V0DS 47 PD61051, 61052 3.2.6 Address 31H 32H 33H 34H Interrupt register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W R/W R/W R/W R/W Interrupt1 Interrupt2 Interrupt3 Interrupt4 Defined by firmware Defined by firmware Defined by firmware Defined by firmware It is set for 1 when the interrupt factor occurs. The interrupt bit clears when host CPU writes 1 in the bit of the interrupt after the interrupt processing. When the other interrupt (which isn't masked) is set to 1 when clearing a interrupt, CINT becomes high 1 s later. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Clear processing continues until interrupt registers is cleared. Address 31H to 34H Bit 7 to 0 Field Firmware define 0: Normal, 1: Interrupt Function Initial value 0H 3.2.7 Address 3EH Reset register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 NBR Bit0 ALL RESET R/W R/W Reset When the host CPU sets 1 to ALL RESET, it resets the inside and it returns to 0 automatically. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Bit 7 to 2 1 NBR Field Reserved (Set 0) Internal CPU reset 0: Normal, 1: Reset 0 ALL RESET Same hardware reset 0: Normal, 1: Reset 0 0 Function Initial value 48 Data Sheet S15082EJ4V0DS PD61051, 61052 3.2.8 Address 35H ROM access cycle register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 iROM2 to iROM0 Bit0 R/W R/W Mask ROM cycle It specifies the access cycle of the instruction ROM of internal CPU when connecting host CPU interface with the serial bus. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 7H. Bit 7 to 3 2 to 0 iROM2 to iROM0 Field Reserved (Set 0) Access cycle of instruction ROM 0: Reserved, 1 to 7: (Setting value+2) by 24.6 MHz 7H Function Initial value 3.2.9 Address 36H Port setup register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ISREQ Bit0 OSVLD R/W R/W Port setup This register sets the active polarity of ISREQ and OSVLD. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Bit 7 to 2 1 ISREQ Field Reserved (Set 0) Active polarity of ISREQ 0: Low active of request, 1: High active of request 0 OSVLD Active polarity of OSVLD/OSRDY 0: Low active of valid/ready 1: High active of valid/ready 0 0 Function Initial value Data Sheet S15082EJ4V0DS 49 PD61051, 61052 4. SYSTEM INTERFACE PROCEDURE The host CPU transfers the firmware of each operation mode to the instruction RAM of the internal CPU and works it. This LSI stores up firmware in SDRAM. Host CPU sets to load the firmware of each operation mode in the instruction RAM of internal CPU from SDRAM. When using a parallel bus interface for the host CPU interface, the host CPU sets a data transfer register after hardware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU and executing. Host CPU writes firmware to SDRAM. When using a serial bus interface for the host CPU interface, the host CPU sets a data transfer register after hardware ware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU from external instruction ROM and executing. Host CPU loads firmware in SDRAM from instruction ROM outside. It stores the firmware of the encoding and the transcode to SDRAM from ROM in case of start-up of the system, and then it can do the changing of a feature at short time by the high-speed transfer of SDRAM. The host CPU sets the mode of the terminal of the PD61051/61052 and the access cycle of ROM to the system interface register after hardware reset and sets the transfer of the instruction of the internal CPU after SDRAM is initialized. 50 Data Sheet S15082EJ4V0DS PD61051, 61052 4.1 Outline An overview from the reset of the hardware to the setting of an operation mode is shown. Initialization Hardware reset SDRAM initialization Note Software reset of internal CPU Reset address (3EH) 02H Instruction download Internal CPU software reset Mode setting Software reset of internal CPU Reset address (3EH) 02H Internal CPU start-up Reset address (3EH) 00H Y Mode change N Operation continuation Note This is not necessary in case that the SDRAM initialization firmware is not separated. Data Sheet S15082EJ4V0DS 51 PD61051, 61052 4.2 Firmware Download The host CPU downloads the firmware at the instruction RAM for the internal CPU. When a host CPU is connected with the serial bus, the firmware can be downloaded from the external ROM for the download processing to speed up. In addition, it stores more than one piece of firmware in the instruction pool area of SDRAM and it can be replaced depending on the need, too. When transferring to the instruction RAM of the internal CPU, the transfer counter register setting value (number of the transfer bytes / 4) is (program size +3)/ 4. 4.2.1 Host CPU to instruction RAM of internal CPU Host CPU transmits the firmware to instruction RAM of the internal CPU. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. Host CPU to instruction RAM of internal CPU Internal CPU reset Reset register (3EH) 02H setting Destination address register (24H to 26H) setting (Program size + 3)/4 Transfer counter register (27H to 29H) setting Host CPUiRAM transfer Transfer mode register (20H)80H setting Transfer data register (3FH) Instruction All instruction written ? N Y Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)00H setting Return 52 Data Sheet S15082EJ4V0DS PD61051, 61052 4.2.2 External ROM to instruction RAM of internal CPU When the host CPU is a serial bus type, CPU transmits the instruction of a mode from external ROM to instruction RAM of Internal CPU. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. External ROM to instruction RAM of internal CPU Internal CPU reset Reset register (3EH) 02H setting ROM access cycle register (35H) setting Source address register (21H to 23H) setting Destination address register (24H to 26H) setting (Program size + 3)/4 Transfer counter register (27H to 29H) setting iROMiRAM transfer Transfer mode register (20H)80H setting Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)00H setting Return Data Sheet S15082EJ4V0DS 53 PD61051, 61052 4.2.3 Host CPU to SDRAM The host CPU can store firmware in the instruction pool area of SDRAM for the internal CPU. It stores more than one piece of firmware and it can be replaced depending on the need, too. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. The number of the transfer bytes is a 4-byte unit. Instruction download Internal CPU reset Reset register (3EH) 02H setting Destination address register (24H to 26H) setting Number of transefer bytes Transfer counter register (27H to 29H) setting Host CPUSDRAM transfer Transfer mode register (20H) 40H setting Transfer data register (3FH) Instruction All instruction writing ending? Y N Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)00H setting N 128 bytes writing ending? Return Y CINT? N Y N Interrupt register 0 (30H): 04H Y Transfer error handling (refer to 4.8) Interrupt register 0 (30H): (02H or 01H) N Y Interrupt register 0 clear Interrupt register 0 (30H) Interrupt register 0 (30H) Return 54 Data Sheet S15082EJ4V0DS PD61051, 61052 4.2.4 External ROM to SDRAM The firmware for the internal CPU can be stored in the firmware cabinet of SDRAM from the external ROM. It stores more than one piece of firmware beforehand and it can be replaced according to need, too. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. When transferring data below the 1k-byte, transfer, dividing every 128 bytes. The number of the transfer bytes is a 4-byte unit. (a) Transfer over 1 Kbytes Instruction download (Serial bus) (b) Transfer below 128 bytes Instruction download (Serial bus) Internal CPU reset Reset register (3EH) 02H setting Internal CPU reset Reset register (3EH) 02H setting Source address register (21H to 23H) setting Source address register (21H to 23H) setting Destination address register (24H to 26H) setting Destination address register (24H to 26H) setting Number of transfer bytes /4 Transfer counter register (27H to 29H) setting Number of transfer bytes /4 Transfer counter register (27H to 29H) setting iROM SDRAM transfer Transfer mode register (20H) 10H setting Interrupt mask0 (2BH) 03H setting iROMSDRAM transfer Transfer mode register (20H) 10H setting Transfer ending (refer to 4.7) After 70 sec Clear mask transfer interrupt Interrupt mask0 (2BH) 00H Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)00H setting Return Internal CPU reset is canceled Reset register (3EH)00H setting Return Data Sheet S15082EJ4V0DS 55 PD61051, 61052 4.3 SDRAM Write during Executing While encoding, the host CPU can transfer parameters to the internal CPU through SDRAM. The number of the transfer bytes is a 4-byte unit. SDRAM writing, during executing Mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Destination address register (24H to 26H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting Host CPU SDRAM transfer Transfer mode register (20H) 02H setting Transfer data register (3FH) Data All data writing ending? Y N N 128 bytes writing ending? Y Transfer ending (refer to 4.7) Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Return CINT? N Y N Interrupt register 0 (30H): 04H Y N Interrupt register 0 (30H): (02H or 01H) Y Interrupt register 0 clear Interrupt register 0 (30H) Interrupt register 0 (30H) Transfer error handling (refer to 4.8) Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Return 56 Data Sheet S15082EJ4V0DS PD61051, 61052 4.4 SDRAM Read during Executing While encoding, the host CPU reads parameters of usable work area of SDRAM. The maximum data of the reading once is 128 bytes. When reading is equal to or more than 128 byte data, execute reading processing repeatedly. The number of the transfer bytes is a 4 bytes unit. SDRAM reading, during executing Mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) settin Source address register (21H to 23H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting SDRAM host CPU transfer Transfer mode register (20H) 01H setting N CINT? Interrupt register 0 clear Interrupt register 0 (30H) Interrupt register 0 (30H) Y Y Interrupt register 0 (30H): (02H or 01H) Transfer data register (3FH)Read data N N Interrupt register 0 (30H): 04H All instructions reading ending? N Y Y Transfer error handling (refer to 4.8) Transfer ending (refer to 4.7) Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Return Return Data Sheet S15082EJ4V0DS 57 PD61051, 61052 4.5 SDRAM Initialization The host CPU transfers the firmware which makes SDRAM a standby condition to the instruction RAM of the internal CPU and executes it. SDRAM initialization SDRAM initialize firmware to instruction RAM of internal CPU 100 s wait Release of software reset of internal CPU Reset register (3EH) 00H N CINT? Y Interrupt register x initialization ending Y Interrupt register x Initialization ending interrupt release N Return 58 Data Sheet S15082EJ4V0DS PD61051, 61052 4.6 Operation Mode Setting by Changing Firmware When changing a mode, host CPU transfers the instruction of each mode from SDRAM to the instruction RAM of the internal CPU and restarts. Mode setting Parameter setting Software reset of internal CPU Reset register (3EH) 02H System interface register setting Mode setting A Source address register (21H to 23H) setting Destination address register (24H to 26H) setting Destination address register (24H to 26H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting Number of transfer bytes/4 Transfer counter register (27H to 29H) setting SDRAM iRAM transfer Transfer mode register (20H) 20H setting Host CPU SDRAM transfer Transfer mode register (20H) 40H setting Transfer ending (refer to 4.7) Transfer data register (3FH) Parameter Internal CPU reset is canceled Reset register (3EH)00H setting All parameters writing ending? Y N Parameter setting Transfer ending (refer to 4.7) Return N 128 bytes writing ending? All parameters in SDRAM writing ending? N Y Y Return Mode setting A CINT? N Y N Interrupt register 0 (30H): 04H Y Transfer error handling (refer to 4.8) Interrupt register 0 (30H): (02H or 01H) N Y Interrupt register 0 clear Interrupt register 0 (30H) Interrupt register 0 (30H) Return Data Sheet S15082EJ4V0DS 59 PD61051, 61052 4.7 Transfer Ending The host CPU confirms a transfer error when the instruction or data transfer ends. The host CPU clears transfer mode and interrupt registers. Transfer ending CINT? N Y N Interrupt register 0 (30H): 01H Y Transfer mode register (20H) 00H setting Interrupt register 0 (30H): 04H Y Interrupt register 0 clear Interrupt register 0 (30H) 01H Transfer error handling (refer to 4.8) N Return 60 Data Sheet S15082EJ4V0DS PD61051, 61052 4.8 4.8.1 Transfer Error Handling Transfer error handling 1 It is the error handling of DMA-ERR which occurs when interrupting the transfers (the host CPU the instruction RAM of internal CPU transfer, the host CPU SDRAM transfer (SSD, SDW), the external ROM SDRAM transfer and the external ROM the instruction RAM of internal CPU transfer) Transfer error handling 1 Set destination address register (24H to 26H) to unused area of SDRAM Transfer counter register (27H to 29H) 04H setting Host CPU SDRAM transfer Transfer mode register (20H) 02H setting Clear the transfer error Interrupt register 0 (30H) 04H setting Transfer data register (3FH) Dummy data All data writing ending? Y N CINT? Y N Interrupt register 0 (30H): 01H Y Host CPU SDRAM transfer release Transfer mode register (20H) 00H setting N Interrupt register 0 (30H) 01H setting Return Data Sheet S15082EJ4V0DS 61 PD61051, 61052 4.8.2 Transfer error handling 2 This is a error handling of DMA-ERR which occurs when interrupting the transfers (SDRAM read during executing and SDRAM instruction RAM of internal CPU transfer) Transfer error handling 2 Destination address register (24H to 26H) Unusing area setting SDRAM host CPU transfer Transfer mode register (20H) 01H setting Transfer counter register (27H to 29H) 04H setting CINT? Host CPU SDRAM transfer Transfer mode register (20H) 02H setting Y N Destination address register (24H to 26H) Unusing area setting N Transfer counter register (27H to 29H) 04H setting Clear transfer error Interrupt register 0 (30H) 04H setting Interrupt register 0 (30H): 02 H Y Transfer data register (3FH) Dummy data Clear Interrupt register 0 Interrupt register 0 (30H) Interrupt register 0 (30H) setting Host CPU SDRAM transfer Transfer mode register (20H) 02H setting All data writing ending? Y Host CPU SDRAM transfer release Transfer mode register (20H) 00H setting N Transfer data register (3FH) Data read Transfer data register (3FH) Dummy data All data reading ending? Y N All data writing ending? Y N Transfer counter register (27H to 29H) 04H setting CINT? Y N CINT? Y N Interrupt register 0 (30H): 01H Y Interrupt register 0 (30H) 01H setting SDRAM host CPU transfer release Transfer mode register (20H) 00H setting N Interrupt register 0 (30H): 01H Y Interrupt register 0 (30H) 01H setting Host CPU SDRAM transfer release Transfer mode register (20H) 00H setting N Return 62 Data Sheet S15082EJ4V0DS PD61051, 61052 4.8.3 Transfer error handling 3 It is the error handling of DMA-ERR which occurs when transfer operation in case of host CPU serial connection with SPI. Transfer error handling 3 SDRAM host CPU transfer Transfer mode register (20H) 01H setting Transfer counter register (27H to 29H) 01H setting SDRAM host CPU transfer Transfer mode register (20H) 01H setting CINT? Transfer data register (3FH) Data read SDRAM host CPU transfer release Transfer mode register (20H) 00H setting Y N Interrupt register 0 (30H): 02H Y Interrupt register 0 (30H) 02H setting N CINT? Y N Transfer data register (3FH) Data read N Interrupt register 0 (30H): 01H Y Interrupt register 0 (30H) 01H setting Transfer data register (3FH) Data read Transfer data register (3FH) Data read Source address register (21H to 23H) setting CINT? Y N Transfer counter register (27H to 29H) 03H setting Interrupt register 0 (30H): 01H Y SDRAM host CPU transfer release Transfer mode register (20H) 00H setting N Interrupt register 0 (30H) 01H Return Data Sheet S15082EJ4V0DS 63 PD61051, 61052 5. EXAMPLE FOR COMMON REGISTER USAGE The PD61051, 61052 operates while the "command code register" is in "start". When "command code register" becomes "start", internal CPU reads parameter registers, then starts the operation. Additionally, internal register sets "status register". Register map for system interface register is defined by firmware. With each application, parameter registers are changed by the firmware. Figure 5-1. Host Interface Register Instruction RAM of Internal CPU Host CPU System Interface Register DMA Controller Internal CPU SDRAM Interface SDRAM PD61051/61052 64 Data Sheet S15082EJ4V0DS PD61051, 61052 5.1 Register Map Example Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 COMCODE ESTS Parameters (Defined by each firmware) SI SSD SDI MSD MI SDW SA19 to SA16 SA15 to SA8 SA7 to SA0 DA16 DA15 to DA8 DA7 to DA0 TC18 to TC16 TC15 to TC8 TC7 to TC0 iCPU-INT DMAERR-M 2CH to 2FH 30H Interrupt Mask (Defined by each firmware) DMA-ERR DMA-RDY DMADONE 31H to 34H 35H 36H 37H to 3DH 3EH NBR ALL RESET 3FH TD7 to TD0 Interrupt (Defined by each firmware) iROM2 to iROM0 ISREQ OSVLD DMARDY-M DMADONE-M SDR Bit0 Address 00H 01H 02H to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH : Reserved Data Sheet S15082EJ4V0DS 65 PD61051, 61052 5.2 5.2.1 Address 00H Example of the Common Register Which A Firmware Defines COMCODE: Command code register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 COMCODE Bit0 The host CPU can change the state of operation to the command code register. The PD61051/61052 accepts commands to operate in three states as shown in the table below. Command Standby / Stop Start Reserved 001 011 Others Code The command which it is possible to set depend on the internal state. In case of the command whose state transfer is possible, the state transfers according to the command. 5.2.2 Address 01H ESTS: Status register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ESTS Bit0 This register shows processing state, when command is illegal, the state doesn't transfer. ESTS Initial State Standby State Encoding State 000 001 011 Code 66 Data Sheet S15082EJ4V0DS PD61051, 61052 Figure 5-2. Command Status Transition Hardware reset Initial State (000) 001 : Standby Standby State (001) 001 : Stop 011 : Start Encoding State (011) Valid Command in Initial State: Valid Command in Standby State: Standby Start Valid Command in Operation State: Stop Data Sheet S15082EJ4V0DS 67 PD61051, 61052 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25C) Parameter Supply Voltage Symbol VDD3 VDD2 Conditions VDD3, vs GND VDD2, vs GND PVDD2, vs PGND Input Voltage Output Voltage Output Current Permissible Loss Operating Ambient Temperature Storage Temperature Tstg -55 to +125 C VIN VOUT IOUT PD TA Vs GND3 Vs GND3 -0.5 to +4.6 -0.5 to +4.6 20 2 0 to +70 V V mA W C Rating 4.6 3.6 Unit V V Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. DC Characteristics (TA = 0 to +70C, VDD3 = 3.30.165 V, VDD2 = 2.50.2 V) Parameter Supply voltage Symbol VDD3 VDD2 Condition VDD3, vs GND VDD2, vs GND PVDD2, vs PGND High-level input voltage Low-level input voltage VIH VIL SCLK Except SCLK High-level output voltage Low-level output voltage Input leakage current VOH VOL ILI Except MD31 to MD0 and CMODE1 Operating current IDD3 IPDD IDD2 3.3 V power supply 2.5 V PLL power supply Internal logic power supply of 2.5 V 70 15 510 mA mA mA 2.2 -0.5 -0.5 2.4 0.4 10 VDD3+0.5 +0.6 +0.7 V V V V V Min. 3.135 2.3 Typ. 3.3 2.5 Max. 3.465 2.7 Unit V V A 68 Data Sheet S15082EJ4V0DS PD61051, 61052 Pin Capacitance (TA = 25C) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Conditions Min. Typ. Max. 20 20 20 Unit pF pF pF AC Characteristics (TA = 0 to +70C, VDD3 = 3.30.165 V, VDD2 = 2.50.2 V, CL = 15 pF, tR = tF = 1 ns) (1) System Parameter SCLK frequency SCLK high-level width SCLK low-level width PSTOP release time1 PSTOP release time2 PSTOP release time3 PSTOP release time4 PSTOP pulse width RESET release time Video input reset time Audio reset time STC reset time Reset pulse width Input rising time Symbol fSCK tSCKH tSCKL tSTP1 tSTP2 tSTP3 tSTP4 tWSTP tRES tlVRES tAURES tSTRES tRESW tIR Vs falling edge of PSTOP After stable IVCLK After stable AMCLK After stable STCLK After stable all clock Vs AMCLK, STCLK, SCLK, ISCLK Vs IVCLK Input falling time tIF Vs AMCLK, STCLK, SCLK, ISCLK Vs IVCLK Output rising time Output falling time tOR tOF 5 3 3 ns ns ns 5 3 ns ns Duty 40:60 Duty 40:60 Vs VDD3 Vs VDD2 Vs PVDD2 Vs SCLK 13.2 13.2 1 1 1 1 1 100 600 600 600 600 3 Conditions Min. Typ. 27.0 Max. Unit MHz ns ns s s s s s s ns ns ns ns ns High level, low level VIH tIR, tOR VIL tIF, tOF Clock input VIH tSCKH VIL tSCKL tSCK = 1/fSCK Data Sheet S15082EJ4V0DS 69 PD61051, 61052 Reset input VDD3 tSTP1 VDD2 tSTP2 PVDD2 tSTP3 Frequency stabilization (10% max. ) SCLK tSTP4 PSTOP tWSTP tRES RESET Caution Notes on power on/off * Apply power to VDD3, and VDD2 and PVDD2 at the same time. * If it is difficult to apply the power to these pins at the same time, apply the power to VDD2 and PVDD2 first. * Cut the power of VDD3, and VDD2 and PVDD2 at the same time. * If it is difficult to cut the power of these pins at the same time, cut the power of VDD2 and PVDD2 last. 70 Data Sheet S15082EJ4V0DS PD61051, 61052 IVCLK tIVRES AMCLK tAURES STCLK tSTRES SCLK tSTP4 PSTOP tWSTP tRES RESET Data Sheet S15082EJ4V0DS 71 PD61051, 61052 IVCLK tIVRES AMCLK tAURES STCLK tSTRES SCLK PSTOP ''L'' tRESW RESET 72 Data Sheet S15082EJ4V0DS PD61051, 61052 (2) Video input interface Parameter IVCLK frequency IVCLK high-level width IVCLK low-level width IVIN7 to IVIN0 setup time IVIN7 to IVIN0 hold time IVVSYNC-input setup time IVVSYNC-input hold time IVHSYNC-input setup time IVHSYNC-input hold time IVFLD-input setup time IVFLD-input hold time Symbol fIVCKS tVCKH tVCKL tIVDS tIVDH tIVVS tIVVH tIVHS tIVHH tIVFS tIVFH Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK Vs rising edge of IVCLK 10 10 5 4 5 4 5 4 5 4 Conditions Min. Typ. 27 Max. Unit MHz ns ns ns ns ns ns ns ns ns ns fIVCKS tIVCKH IVCLK tIVDS tIVDH tIVCKL IVIN7 to IVIN0 Cr Y Cb Y Cr tIVVH tIVHH tIVFH IVHSYNC IVVSYNC IVFLD tIVVS tIVHS tIVFS Data Sheet S15082EJ4V0DS 73 PD61051, 61052 (3) Video output interface Parameter OVCLK frequency OVCLK high-level width OVCLK low-level width OVOUT7 to OVOUT0 hold time OVOUT7 to OVOUT0 delay time OVVSYNC hold time OVVSYNC delay time OVHSYNC hold time OVHSYNC delay time tOVVHO tOVVD tOVHHO tOVHD Vs rising edge of OVCLK Vs rising edge of OVCLK Vs rising edge of OVCLK Vs rising edge of OVCLK 7 28 7 28 ns ns ns ns tOVDO Vs rising edge of OVCLK 28 ns Symbol fOVCKS tOVCKH tOVCKL tOVHO Vs rising edge of OVCLK 8 8 7 Conditions Min. Typ. 27 Max. Unit MHz ns ns ns fOVCKS tOVCKH OVCLK tOVDO tOVHO tOVCKL OVOUT7 to OVOUT0 Y Cb Y Cr tOVVD tOVHD tOVVHO tOVHHO OVHSYNC OVVSYNC 74 Data Sheet S15082EJ4V0DS PD61051, 61052 (4) Audio input interface Parameter Bit data-in setup time Bit data-in hold time LRCK-in setup time LRCK-in hold time Symbol tACDS tACDH tACLS tACLH Vs IABCK Vs IABCK Vs IABCK Vs IABCK Conditions Min. 37 37 100 37 Typ. Max. Unit ns ns ns ns IABCK tACDS tACDH IABD tACLH tACLS IALRCK Data Sheet S15082EJ4V0DS 75 PD61051, 61052 (5) Audio output interface Parameter Bit data-out hold time Bit data-out delay time LRCK-out hold time LRCK-out delay BCK-out duty ratio AMCLK duty ratio AMCLK frequency Symbol tACDHO tACDD tACLHO tACLD dBCK dAMCLK fAMCLK Conditions Vs OABCK Vs OABCK Vs OABCK Vs OABCK 50 50 18.432 -5 25 Min. -5 25 Typ. Max. Unit ns ns ns ns % % MHz OABCK tACDHO tACDD OABD tACLHO tACLD OALRCK 76 Data Sheet S15082EJ4V0DS PD61051, 61052 (6) Stream input interface (a) Parallel stream input Valid mode Parameter ISCLK cycle ISCLK low-level width ISCLK high-level width ISREQ output hold time ISVLD setup time ISVLD hold time ISSYNC setup time ISSYNC hold time IS7 to IS0 setup time IS7 to IS0 hold time Data cycle time Symbol tISCcyc tISCLW tISCHW tISRQHO tISVS tISVH tISSS tISSH tISDS tISDH tDCYC Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Conditions Min. 80 37 37 0 7 3 7 3 7 3 80 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns Remark ISREQ is effective only when it works by the master mode. ISREQ becomes invalid asynchronously to ISCLK. ISREQ output delay time doesn't prescribe to ISCLK. ISCLK (I) tISCLW ISREQ (O) tISVS ISVLD (I) tISVH IS7 to IS0 (I) No received data tISCHW tISCYC tISRQHO tDCYC Valid data Valid data Valid data Valid data tISDH Valid data Valid data Valid data Valid data 1st of packet tISSH ISSYNC (I) tISSS tISDS Remark ISSYNC is active high, SREQ is active high and ISCLK is active high edge. Data Sheet S15082EJ4V0DS 77 PD61051, 61052 Strobe mode Parameter ISSTB low-level width ISSTB high-level width ISREQ output hold time ISSYNC setup time ISSYNC hold time IS7 to IS0 setup time IS7 to IS0 hold time Data cycle time Symbol tISSTLW tISSTHW tISRQHO tISSS tISSH tISDS tISDH tDCYC Vs active edge of ISSTB Vs active edge of ISSTB Vs active edge of ISSTB Vs active edge of ISSTB Vs active edge of ISSTB Conditions Min. 37 37 0 7 3 7 3 80 Typ. Max. Unit ns ns ns ns ns ns ns ns Remark ISREQ becomes invalid asynchronously to ISSTB. ISREQ output delay time doesn't prescribe to ISSTB. ISREQ (O) tISSTHW ISSTB (I) tISSTLW IS7 to IS0 (I) No received data tISRQHO tDCYC Valid data Valid data Valid data tISDH Valid data Valid data Valid data Valid data 1st of packet Valid data tISSH ISSYNC (I) tISSS tISDS Remark ISSYNC is active high, ISREQ is active low and ISSTB is active high edge. 78 Data Sheet S15082EJ4V0DS PD61051, 61052 (b) Serial stream input Parameter ISCLK period ISCLK low-level width ISCLK high-level width ISVLD setup time ISVLD hold time ISSYNC setup time ISSYNC hold time ISERR setup time ISERR hold time IS0 setup time IS0 hold time Symbol tISSCW tISSCLW tISSCHW tISSVS tISSVH tISSSS tISSSH tISSES tISSEH tISSDS tISSDH Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Vs active edge of ISCLK Conditions Min. 15.6 5.0 5.0 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns Remark Setup and hold time provide to the activist edge of ISCLK. tISSCW tISSCLW tISSCHW ISCLK tISSDS IS0 tISSDH tISSVS ISVLD tISSVH tISSSS ISSYNC tISSSH tISSES ISERR tISSEH Remark ISCLK is active high edge. Data Sheet S15082EJ4V0DS 79 PD61051, 61052 (7) Stream output interface (a) Parallel stream data output Valid and master mode Parameter OSCLK low-level width Symbol tOSCLW Conditions Active rising edge Active falling edge OSCLK high-level width tOSCHW Active rising edge Active falling edge OSVLD hold time OSVLD delay time OSSYNC hold time OSSYNC delay time OS7 to OS0 hold time OS7 to OS0 delay time Data cycle time tOSVHO tOSVD tOSSHO tOSSD tOSDHO tOSDD tDCYC2 Vs active edge of OSCLK Vs non active edge of OSCLK Vs active edge of OSCLK Vs non active edge of OSCLK Vs active edge of OSCLK Vs non active edge of OSCLK Min. 30 70 70 30 30 -5 30 -5 30 -5 105 +5 +5 +5 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns Remark OSVLD is active high, OSSYNC is active high and OSCLK is active high edge. OSCLK tOSVD tOSCHW OSVLD 188 bytes tOSVHO Valid data Valid data Valid data Valid data tDCYC2 Valid data Valid data Valid data tOSDHO tOSCLW OS7 to OS0 Invalid data Invalid data 1st of packet tOSSD OSSYNC tOSSHO tOSDD 80 Data Sheet S15082EJ4V0DS PD61051, 61052 Strobe and byte mode Parameter OSREQ high-level time OSSTB high-level width Symbol tOSRHW tOSSTHW Active rising edge Active falling edge OSSTB low-level width tOSSTLW Active rising edge Active falling edge OSREQ hold time OSREQ hold time tOSRRD tOSTRQ1 tOSTRQ2 OSSTB delay time tOSRSTD1 tOSRSTD2 OSRDY delay time OSSYNC-out delay time OSSYNC-out hold time OS7 to OS0 out delay time OS7 to OS0 out hold time tOSSTRD1 tOSSD tOSSHO tOSDD tOSDHO Vs active edge of OSRDY Vs active edge of OSSTB Vs non active edge of OSSTB Vs active edge of OSREQ Vs non active edge of OSREQ Vs non active edge of OSSTB Vs non active edge of OSSTB Vs active edge of OSSTB Vs non active edge of OSSTB Vs active edge of OSSTB -5 70 -5 70 +5 Conditions Min. 2 100 70 70 100 0 0 0 2 3 3 +5 3 Typ. Max. Unit STCLK ns ns ns ns ns ns ns STCLK STCLK STCLK ns ns ns ns OSRDY tOSRRD tOSRHW tOSTRQ1 tOSSTRD1 OSREQ tOSTRQ2 tOSRSTD1 tOSRSTD2 OSSTB tOSSTLW tOSDD tOSSTHW OS7-OS0 tOSDHO tOSSD OSSYNC tOSSHO Remark OSSYNC is active high, OSRDY is active low and OSSTB is active high edge. Data Sheet S15082EJ4V0DS 81 PD61051, 61052 (b) Serial stream data output Parameter OSCLK period OSCLK low-level width OSCLK high-level width OS0 delay time OS0 hold time OSVLD delay time OSVLD hold time OSSYNC delay time OSSYNC hold time Symbol tOSSCW tOSSCLW tOSSCHW tOSSDD tOSSDHO tOSSVD tOSSVHO tOSSSD tOSSSHO Vs active edge of OSCLK Vs active edge of OSCLK Vs active edge of OSCLK Vs active edge of OSCLK Vs active edge of OSCLK Vs active edge of OSCLK 5.0 5.0 27 5.0 27 10 10 27 Conditions Min. Typ. 37 Max. Unit ns ns ns ns ns ns ns ns ns Remarks 1. Active edge of OSCLK is able to change according to the following circuit. 2. Period of the OSCLK is provided by STCLK. tOSSCW tOSSCLW tOSSCHW OSCLK tOSSD OS0 tOSSDHO tOSSVD OSVLD tOSSHO tOSSSD OSSYNC tOSSSHO Remark OSCLK is active high edge. 82 Data Sheet S15082EJ4V0DS PD61051, 61052 (8) SDRAM interface Parameter MCLK cycle time MCLK high-level width MCLK low-level width MD31 to MD0-out hold time MD31 to MD0-out delay time MD31 to MD0 low-Z output time MD31 to MD0 high-Z output time MD31 to MD0-in setup time MD31 to MD0-in hold time MA13 to MA0 delay time MA13 to MA0 hold time MCLKE delay time MCLKE hold time Command delay time Command hold time ACT REF/ACT command period REF REF/ACT command period ACT PRE command period PRE ACT command period ACT R/W command delay time ACT (0) ACT (1) command period Data-in to PRE command period Data-in to ACT (REF) command period (Auto pre-charge) Mode register set cycle period Refresh Time (4096 refresh cycle) tRSC tREF 2 50 MCLK ms tDPL tDAL 2 6 MCLK MCLK Symbol tCK tCH tCL tOH tOD tLZ tHZ tDS tDH tAD tAH tCKS tCKH tCMD tCMH tRC tRC1 tRAS tRP tRCD tRRD Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK Vs MCLK 1.5 12 12 12 12 3 4 1.5 9 1.5 9 6 2 9 0 9 3.5 3.5 1.5 9 Conditions Min. Typ. 12.3 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MCLK MCLK MCLK MCLK MCLK MCLK Remark REF: Refresh, ACT: Active, PRE: Pre-charge Data Sheet S15082EJ4V0DS 83 84 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tCL tCMH tCKH tAH tCK tDS tRCD tRAS tRC tDH tRP Hi-Z Read command for bank A Precharge command for bank A Active command for bank A T0 tCK MCLK tCH MCLKE tCMD MCS MRAS MCAS MWE MA13 Read timing (Manual pre-charge, burst length = 4, CAS latency = 3) Data Sheet S15082EJ4V0DS MA12 MA10 MA9 to MA0 MDQM tAD Low MD31 to MD0 Hi-Z PD61051, 61052 Active command for bank A T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tCK MCLK tCL tCMH tCKH tCH MCLKE tCMD MCS MRAS MCAS MWE MA13 Read timing (Auto pre-charge, burst length = 4, CAS latency = 3) Data Sheet S15082EJ4V0DS MA12 MA10 MA9 to MA0 tAH tCK MDQM tAD Low MD31 to MD0 tRCD tRAS tRRD Hi-Z tDS tDH tRC Hi-Z Active command for bank A Read with Auto Precharge command for bank A Active command for bank B Active command for bank A PD61051, 61052 85 86 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tCK tCL tCMH tCKH tCKD tCMD T14 T15 T16 T17 T18 T19 T20 T21 tCH tAD Low tAH tLZ Hi-Z DAa1 DAa2 DAa3 DAa4 DBa1 MCLK MCLKE MCS MRAS MCAS Write timing (Burst length = 4, CAS latency = 3) MWE MA13 MA12 Data Sheet S15082EJ4V0DS MA10 MA9 to MA0 MDQM tOH tOD tHZ DBa2 DBa3 DBa4 MD31 to MD0 tRCD tRRD tRC tRCD Hi-Z tDAL tRAS tRC tDPL tRP Active command for bank A Active command for bank B Precharge command for bank B Active command for bank A Active command of bank B Write with Auto Precharge command for bank B PD61051, 61052 Write with Auto Precharge command for bank A PD61051, 61052 (9) Host CPU interface (a) Parallel bus interface: Wait mode (1/2) Parameter CCS CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Do not care CCS CWAIT delay time tCWAD1 Vs falling edge of CCS CCS later than CRE/CWE CCS CWAIT release time tCRDY Vs falling edge of CCS CCS later than CRE/CWE CA5 to CA0 CRE delay time CCS CRE delay time CRE CWAIT delay time CRE CWAIT release time CCS CD7 to CD0 low-Z time tARD tCRD tRWD1 tRRD tCDLD Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CRE Vs falling edge of CRE Vs falling edge of CCS Data not fixed CRE CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS CD7 to CD0 delay time tCDD Vs falling edge of CCS Data fixed CRE CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE CD7 to CD0 hold time tRDH Vs rising edge of CRE Earlier than rising edge of CCS CRE CA5 to CA0 hold time CRE CCS hold time CCS CD7 to CD0 hold time tRAH tRCH tCDRH Vs rising edge of CRE Vs rising edge of CRE Vs rising edge of CCS Earlier than rising edge of CRE CD7 to CD0 CWAIT release time CD7 to CD0 Hi-Z delay time CA5 to CA0 CWE delay time CCS CWE delay time CWE CWAIT delay time CWE CWAIT release time CWE CD7 to CD0 delay time tCDZD tAWD tCWD tWWD1 tWRD tWDD Vs rising edge of CRE or CCS Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CWE Vs falling edge of CWE Vs falling edge of CWE Until data fixed CWE CD7 to CD0 hold time tWDH Vs rising edge of CWE -7 ns -28 -20 15 150 30 12 ns ns ns ns ns ns tCDW Vs CD7 to CD0 fixed 10 ns -27 -27 0 ns ns ns 0 ns 150 ns 150 ns 0 ns 0 -20 -20 15 175 ns ns ns ns ns 175 ns 15 ns Min. Typ. Max. Unit ns Data Sheet S15082EJ4V0DS 87 PD61051, 61052 (2/2) Parameter CWE CA5 to CA0 hold time CWE CCS hold time CCS CD7 to CD0 hold time CCS CWAIT release time CWAIT release CWE/CRE hold time CWAIT release CD5 to CD0 hold time CWAIT release CSS hold time CRE/CWE recovery time Access cycle after other device Symbol tWAH tWCH tCDWH tCWAD2 tCWR tCWA tCWC tCAC tCCYC Conditions Vs rising edge of CWE Vs rising edge of CWE Vs rising edge of CCS Vs rising edge of CCS Vs CWAIT release Vs CWAIT release Vs CWAIT release Min. -27 -27 0 0 0 0 0 25 200 15 Typ. Max. Unit ns ns ns ns ns ns ns ns ns Remark If CCS change to "H" in wait cycle, it cancels CWAIT. In access time, don't make CCS "H" until wait released. 88 Data Sheet S15082EJ4V0DS PD61051, 61052 Wait mode (Wait active low, read cycle) tCWA CA5 to CA0 tARD CCS tCAD CD7 to CD0 tCDLD CRE tCAC CWE tCRDY CWAIT tCWAD1 tRWD1 tRRD tCDD tCAC tCDW tCDRH tRDLD tRDD tRDH tCDZD tCRD tCWC tRAH tRCH tCDZD tCWR Wait mode (Wait active low, write cycle) tCWA CA5 to CA0 tAWD CCS tCAD tCDWH CD7 to CD0 tWDH CRE tCWD tCWC tWAH tWCH CWE tCAC tWDD tCRDY tCAC tWDD tCWR tWRD CWAIT tCWAD1 tWWD1 Data Sheet S15082EJ4V0DS 89 PD61051, 61052 Wait mode (Wait active high, read cycle) tCWA CA5 to CA0 tARD CCS tCAD CD7 to CD0 tCDLD CRE tCAC CWE tCRDY CWAIT tCWAD1 tRWD1 tRRD tCDD tCAC tCDW tCDRH tRDLD tRDD tRDH tCDZD tCRD tCWC tRAH tRCH tCDZD tCWR Wait mode (Wait active high, write cycle) tCWA CA5 to CA0 tAWD CCS tCAD tCDWH CD7 to CD0 tWDH CRE tCWD tCWC tWAH tWCH CWE tCAC tWDD tCRDY tCAC tWDD tCWR tWRD CWAIT tCWAD1 tWWD1 90 Data Sheet S15082EJ4V0DS PD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT Data Sheet S15082EJ4V0DS 91 PD61051, 61052 (b) Parallel bus interface: Ready mode (1/2) Parameter CCS CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Do not care CCS CWAIT delay time tCWAD1 Vs falling edge of CCS CCS later than CRE/CWE CCS CWAIT ready time tCRDY Vs falling edge of CCS CCS later than CRE/CWE CA5 to CA0 CRE delay time CCS CRE delay time CRE CWAIT ready time CCS CD7 to CD0 low-Z time tARD tCRD tRRD tCDLD Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CRE Vs falling edge of CCS Data not fixed CRE CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS CD7 to CD0 delay time tCDD Vs falling edge of CCS Data fixed CRE CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE CD7 to CD0 hold time tRDH Vs rising edge of CRE Earlier than rising edge of CCS CRE CA5 to CA0 hold time CRE CCS hold time CCS CD7 to CD0 hold time tRAH tRCH tCDRH Vs rising edge of CRE Vs rising edge of CRE Vs rising edge of CCS Earlier than rising edge of CRE CD7 to CD0 CWAIT ready time CD7 to CD0 high-Z delay time CA5 to CA0 CWE delay time CCS CWE delay time CWE CWAIT ready time CWE CD7 to CD0 delay time tCDZD tAWD tCWD tWRD tWDD Vs rising edge of CRE or CCS Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CWE Vs falling edge of CWE Until data fixed CWE CD7 to CD0 hold time CWE CA5 to CA0 hold time CWE CCS hold time CCS CD7 to CD0 hold time CRE CWAIT release time tWDH tWAH tWCH tCDWH tRWD2 Vs rising edge of CWE Vs rising edge of CWE Vs rising edge of CWE Vs rising edge of CCS Vs rising edge of CRE -7 -27 -27 0 0 15 ns ns ns ns ns -28 -20 150 30 12 ns ns ns ns ns tCDW Vs CD7 to CD0 fixed 10 ns -27 -27 0 ns ns ns 0 ns 150 ns 150 ns 0 ns 0 -20 -20 175 ns ns ns ns 175 ns 15 Min. Typ. Max. Unit ns 92 Data Sheet S15082EJ4V0DS PD61051, 61052 (2/2) Parameter CWE CWAIT release time CCS CWAIT release time CWAIT ready CWE/CRE hold time CWAIT ready CA5 to CA0 hold time CWAIT ready CCS hold time CRE/CWE recovery time Access cycle after other device tCWC tCAC tCCYC Vs CWAIT ready 0 25 200 ns ns ns tCWA Vs CWAIT ready 0 ns Symbol tWWD2 tCWAD2 tCWR Conditions Vs rising edge of CWE Vs rising edge of CCS Vs CWAIT ready Min. 0 0 0 Typ. Max. 15 15 Unit ns ns ns Remark If CCS change to "H" in wait cycle, it cancels CWAIT. In access time, don't make CCS "H" until wait becomes ready. Data Sheet S15082EJ4V0DS 93 PD61051, 61052 Ready mode (Ready active high, read cycle) tCWA CA5 to CA0 tARD CCS tCAD CD7 to CD0 tCDLD CRE tCAC CWE tCRDY CWAIT tCWAD2 tRWD2 tRRD tCDD tCAC tCDW tCDRH tRDLD tRDD tRDH tCDZD tCRD tCWC tRAH tRCH tCDZD tCWR Ready mode (Ready active high, write cycle) tCWA CA5 to CA0 tAWD CCS tCAD tCDWH CD7 to CD0 tWDH CRE tCWD tCWC tWAH tWCH CWE tCAC tWDD tCRDY tCAC tWDD tCWR tWRD CWAIT tCWAD2 tWWD2 94 Data Sheet S15082EJ4V0DS PD61051, 61052 Ready mode (Ready active low, read cycle) tCWA CA5 to CA0 tARD CCS tCAD CD7 to CD0 tCDLD CRE tCAC CWE tCRDY CWAIT tCWAD2 tRWD2 tRRD tCDD tCAC tCDW tCDRH tRDLD tRDD tRDH tCDZD tCRD tCWC tRAH tRCH tCDZD tCWR Ready mode (Ready active low, write cycle) tCWA CA5 to CA0 tAWD CCS tCAD tCDWH CD7 to CD0 tWDH CRE tCWD tCWC tWAH tWCH CWE tCAC tWDD tCRDY tCAC tWDD tCWR tWRD CWAIT tCWAD2 tWWD2 Data Sheet S15082EJ4V0DS 95 PD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT 96 Data Sheet S15082EJ4V0DS PD61051, 61052 (c) Parallel bus interface: Fixed wait mode Parameter CCS CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Do not care CRE pulse width CA5 to CA0 CRE delay time CCS CREdelay time CCS CD7 to CD0 low-Z time tRW tARD tCRD tCDLD Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CCS Data not fixed CRE CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS CD7 to CD0 delay time tCDD Vs falling edge of CCS Data fixed CRE CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE CD7 to CD0 hold time tRDH Vs rising edge of CRE Earlier than rising edge of CCS CRE CA5 to CA0 hold time CRE CCS hold time CCS CD7 to CD0 hold time CD7 to CD0 high-Z delay time CWE pulse width CA5 to CA0 CWE delay time CCS CWE delay time CWE CD7 to CD0 delay time tFRAH tFRCH tCDRH tCDZD tWW tAWD tCWD tWDD Vs CA5 to CA0 Vs falling edge of CCS Vs falling edge of CWE Until data fixed CWE CD7 to CD0 hold time CWE CA5 to CA0 hold time CWE CCS hold time CCS CD7 to CD0 hold time CRE/CWE recovery time Access cycle after other device tWDH tFWAH tFWCH tCDWH tCAC tCCYC Vs rising edge of CWE Vs rising edge of CWE Vs rising edge of CWE Vs rising edge of CCS -7 -27 -27 0 25 200 ns ns ns ns ns ns Vs rising edge of CRE Vs rising edge of CRE Vs rising edge of CCS Vs rising edge of CRE or CCS 150 -28 -20 30 -27 -27 0 12 ns ns ns ns ns ns ns ns 0 ns 150 ns 150 ns 0 ns 175 -20 -20 0 ns ns ns ns Min. Typ. Max. Unit ns Data Sheet S15082EJ4V0DS 97 PD61051, 61052 Fixed wait mode (Read cycle) CA5 to CA0 tARD CCS tCAD CD7 to CD0 tCDLD CRE tCAC CWE tCDD tCAC tCDRH tRDLD tRDD tRW tRDH tCDZD tCRD tFRAH tFRCH tCDZD Fixed wait mode (Write cycle) CA5 to CA0 tAWD CCS tCAD tCDWH CD7 to CD0 tWDH CRE tCWD tFWAH tFWCH CWE tCAC tWDD tCAC tWDD tWW 98 Data Sheet S15082EJ4V0DS PD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE Data Sheet S15082EJ4V0DS 99 PD61051, 61052 (10) Serial bus interface (a) Serial bus interface Parameter CCS CSCLK delay time CCS CSDI delay time CSDI setup time CSDI hold time CSDO hold time CSDO delay time CSCLK CCS hold time CCS high-level width CSCLK cycle time CSCLK high-level width CSCLK high-level width Symbol tCSCK tCSDI tCSDS tCSDH tCSDHO tCSDD tCCKS tCSHW tCKCYC tCSCHW tCSCLW Conditions Vs falling edge of CCS Vs falling edge of CCS Vs rising edge of CSCLK Vs rising edge of CSCLK Vs falling edge of CSCLK Vs falling edge of CSCLK Vs rising edge of CSCLK 75 125 100 40 40 Min. 10 10 10 10 0 15 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns CCS tCSCK CSCLK tCSCLW tCSCHW tCKCS CSDI tCSDI tCSDS tCSDH CSDO tCSDHO tCSDD 100 Data Sheet S15082EJ4V0DS PD61051, 61052 [Data Write] CCS tCSCK CSCLK tCSDI CSDI CSDO xx A5 A4 A3 A2 A1 A0 W x xx tCSDS tCSDH [Data Read] CCS tCSCK CSCLK tCSDI CSDI CSDO xx A5 A4 A3 A2 A1 A0 xx tCSDS tCSDH R x x x x x x x x x x tCSDS tCSDH tCKCS tCSHW D7 D6 D5 D4 D3 D2 D1 D0 x tCKCS tCSHW tCKCYC tCKCYC D7 D6 D5 D4 D3 D2 D1 D0 tCSDHO tCSDD (b) Instruction ROM interface Parameter Address setup time Address hold time FOE low-level width FOE high-level width Data setup time Data hold time Data high-Z output time Symbol tFARS tFARH tFRLW tFRHW tFDS tFDH tFDHL Vs rising edge of FOE Vs rising edge of FOE Vs rising edge of FOE Conditions Vs falling edge of FOE Vs rising edge of FOE Min. 0 5 70 24 25 0 60 225 Typ. Max. Unit ns ns ns ns ns ns ns FA19 to FA0 tFARH tFARS tFRHW FOE tFRLW FD7 to FD0 Hi-Z tFDS tFDH Hi-Z tFDHL Hi-Z Data Sheet S15082EJ4V0DS 101 PD61051, 61052 7. PACKAGE DRAWING 208-PIN PLASTIC QFP (FINE PITCH) (28x28) A B 156 157 105 104 detail of lead end S CD Q R 208 1 53 52 F G P H I M J K M S L NS NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 30.60.2 28.00.2 28.00.2 30.60.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.30.2 0.50.2 0.17 +0.03 -0.07 0.10 3.20.1 0.40.1 55 3.8 MAX. P208GD-50-LML,MML,SML,WML-7 102 Data Sheet S15082EJ4V0DS PD61051, 61052 8. RECOMMENDED SOLDERING CONDITIONS The PD61051, 61052 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 8-1. Surface-Mounted Soldering Conditions PD61051GD-LML: Note1 PD61051GD-LML-A : PD61052GD-LML: Note1 PD61052GD-LML-A : Soldering Method 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) 208-pin plastic QFP (Fine pitch) (28x28) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C Time: 30 sec. max. (at 210C or higher) Count: Three times or fewer Exposure limit: 7 days Note2 IR35-207-3 (After that, prebake at 125C for 20 to 72 hours) VP15-207-3 VPS Package peak temperature: 215C Time: 40 sec. max. (at 200C or higher) Count: Three times or fewer Exposure limit: 7 days Note2 (After that, prebake at 125C for 20 to 72 hours) Partial heating Pin temperature: 300C max. Time: 3 sec. max. (per pin row) Notes 1. Lead-free product 2. After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use two or more soldering methods in combination (except for partial heating method). Data Sheet S15082EJ4V0DS 103 PD61051, 61052 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 104 Data Sheet S15082EJ4V0DS PD61051, 61052 [MEMO] Data Sheet S15082EJ4V0DS 105 PD61051, 61052 Dolby is a trademark of Dolby Laboratories. * The information in this document is current as of November, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 |
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